NXP Semiconductors MCF5253, Reference Manual

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MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 22-1
Chapter 22
USB, ATA DMA, and Clock Integration Module
This chapter includes the memory map, register descriptions and functional description of the ATA DMA
integration module.
22.1 Introduction
This chapter includes registers that are used to configure the various modules that are new to the MCF5253
family. It also includes a shared 16 kB local memory for the ATA and USB modules.
22.2 Memory Map and Register Definitions
Table 22-1 provides the memory map and register definitions for the ATA DMA integration module.
22.2.1 Miscellaneous Configuration Register (MISCCR)
Table 22-1. Real Time Clock Memory Map
MBAR2
Offset
Register Access Reset Value Section/Page
0x500 Miscellaneous Configuration Register (MISCCR) R/W Undefined 22.2.1/22-1
0x504 ATA DMA Source and Destination Address Register (ATA_DADDR) R/W 0x0000_0000 22.2.2/22-3
0x508 ATA DMA Count Register (ATA_DCOUNT) R/W 0x0000_0000 22.2.3/22-3
0x50C RTC Time Register (RTC_TIME) R Undefined 26.3.2/26-2
0x510 USB/FlexCAN Clock Gating (USBCANCLK) R/W 0x0000_0000 22.2.5/22-4
Offset: MBAR2 0x500 (MISCCR) Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R URIP 0
URIE
RTCPL RTC
CLR
DMA
END
CPU
END
ADIP
ADIE ADTD ADTA
W URIC ADIC
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 22-1. Miscellaneous Configuration Register (MISCCR)