NXP Semiconductors MCF5253, Reference Manual

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Universal Serial Bus Interface
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 24-59
11–10 Cerr Error Counter. This field is a 2-bit down counter that keeps track of the number of consecutive errors
detected while executing this qTD. If this field is programmed with a non-zero value during set-up, the host
controller decrements the count and writes it back to the qTD if the transaction fails. If the counter counts
from one to zero, the host controller marks the qTD inactive, sets the Halted bit to a one, and error status
bit for the error that caused Cerr to decrement to zero. An interrupt will be generated if the USB Error
Interrupt Enable bit in the USBINTR register is set. If the host controller driver (HCD) software programs
this field to zero during set-up, the host controller will not count errors for this qTD and there will be no limit
on the retries of this qTD.
Note: Write-backs of intermediate execution state are to the queue head overlay area, not the qTD.
Error Decrement Counter
Transaction
Error Yes
Data Buffer
Error No
.
Data buffer errors are host problems. They don't count against the device's retries.
Note: The software must not program Cerr to a value of zero when the EPS field is
programmed with a value indicating a Full- or Low-speed device. This combination
could result in undefined behavior.
Stalled
No
.
Detection of Babble or Stall automatically halts the queue head. Thus, count is not
decremented
Babble
Detected
No
.
Detection of Babble or Stall automatically halts the queue head. Thus, count is not
decremented
No Error
No
.
If the EPS field indicates a HS device or the queue head is in the Asynchronous
Schedule (and PIDCode indicates an IN or OUT) and a bus transaction completes and the
host controller does not detect a transaction error, then the host controller should reset Cerr
to extend the total number of errors for this transaction. For example, Cerr should be reset
with maximum value (0b11) on each successful completion of a transaction. The host
controller must never reset this field if the value at the start of the transaction is 0b00.
9–8 PID Code This field is an encoding of the token, which should be used for transactions associated with this transfer
descriptor. Encodings are:
00 OUT Token generates token (E1H)
01 IN Token generates token (69H)
10 SETUP Token generates token (2DH) (undefined if endpoint is an Interrupt transfer type, for example.
µFrame S-mask field in the queue head is non-zero.)
11 Reserved.
Table 24-53. qTD Token (DWord 2) (continued)
Bit Name Description