NXP Semiconductors MCF5253, Reference Manual

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DMA Controller
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 14-17
the BCR may skip over the programmed boundary. In this case, the DMA bus request will not be negated.
If the BWC = 000, the request signal will remain asserted until the BCR reaches zero. In addition, will
assert to indicate that the channel has been programmed to have priority.
NOTE
In this arbitration scheme, the arbiter can always force the DMA to
relinquish the bus.
14.7.3 Channel Termination
14.7.3.1 Error Conditions
When the bus encounters a read or write cycle that terminates with an error condition, the appropriate bit
of the DSR is set, depending on whether the bus cycle was a read (BES) or a write (BED). The DMA
transfers are then halted. If the error condition occurred during a write cycle, any data remaining in the
internal holding register is lost.
14.7.3.2 Interrupts
If the INT bit of the DCR is set, the DMA will drive the appropriate slave bus interrupt signal. The
processor can then read the DSR to determine if the transfer terminated successfully or with an error. The
DONE bit of the DSR is then written with a 1 to clear the interrupt, along with clearing the DONE and
error bits.