NXP Semiconductors MCF5253, Reference Manual, Page: 151 / 648

System Integration Module (SIM)
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 9-7
• UART0 and UART1 modules
• DMA modules
• QSPI module
The secondary interrupt controller is decentralized, and services the following:
• GPIO interrupts
• Audio interface module
• MemoryStick/SD module
• AD convertor module
• I
2
C1 module
• Software triggered Interrupts
• FlexCAN modules
• USB module
• ATA module
• UART2 module
9.4.1 Primary Interrupt Controller Registers
Primary internal interrupt sources have their own interrupt control registers ICR[11:0], IPR, and IMR.
Table 9-5 gives the location and description of each ICR.
Primary interrupts are programmed to a level and priority. All primary interrupts have a unique Interrupt
Control Register (ICR). There are 28 possible priority levels, for the primary interrupts.
Table 9-5. Primary Interrupt Control Register Memory Map
Address Name Width Description Reset Value Access
MBAR + $04C ICR0 8 SWT $00 R/W
MBAR + $04D ICR1 8 TIMER 0 $00 R/W
MBAR + $04E ICR2 8 TIMER 1 $00 R/W
MBAR + $04F ICR3 8 I
2
C0 $00 R/W
MBAR + $050 ICR4 8 UART 0 $00 R/W
MBAR + $051 ICR5 8 UART 1 $00 R/W
MBAR + $052 ICR6 8 DMA 0 $00 R/W
MBAR + $053 ICR7 8 DMA 1 $00 R/W
MBAR + $054 ICR8 8 DMA 2 $00 R/W
MBAR + $055 ICR9 8 DMA 3 $00 R/W
MBAR + $056 ICR10 8 QSPI $00 R/W
MBAR + $057 ICR11 8 Reserved – –