NXP Semiconductors MCF5253, Reference Manual

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Background Debug Mode (BDM) Interface
MCF5253 Reference Manual, Rev. 1
20-2 Freescale Semiconductor
20.1.1 Breakpoint (BKPT)
The BKPT active-low input signal is used to request a manual breakpoint. Its assertion causes the processor
to enter a halted state after the completion of the current instruction. The halt status is reflected on the
processor status (PST) pins as the value $F.
20.1.2 Debug Data (DDATA[3:0])
These output signals display the hardware register breakpoint status as a default, or optionally, captured
address and operand values. The capturing of data values is controlled by the setting of the
configuration/status register (CSR). Additionally, execution of the WDDATA instruction by the processor
captures operands which are displayed on DDATA. These signals are updated each processor cycle.
20.1.3 Development Serial Clock (DSCLK)
This input signal is synchronized internally and provides the clock for the serial communication port to the
debug module. The maximum frequency is 1/5 the speed of the processor’s clock (CLK). At the
synchronized rising edge of DSCLK, the data input on DSI is sampled, and the DSO output changes state.
See
Figure 20-3 for more information.
20.1.4 Development Serial Input (DSI)
The input signal is synchronized internally and provides the data input for the serial communication port
to the debug module.
20.1.5 Development Serial Output (DSO)
This signal provides serial output communication for the debug module responses.
20.1.6 Processor Status (PST[3:0])
These output signals report the processor status. Table 20-1 shows the encoding of these signals. These
outputs indicate the current status of the processor pipeline and are not related to the current bus transfer.
The PST value is updated each processor cycle.