NXP Semiconductors MCF5253, Reference Manual

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Universal Serial Bus Interface
MCF5253 Reference Manual, Rev. 1
24-74 Freescale Semiconductor
24.9.7 Periodic Schedule
The periodic schedule traversal is enabled or disabled via the Periodic Schedule Enable bit in the
USBCMD register. If the Periodic Schedule Enable bit is cleared, then the host controller simply does not
try to access the periodic frame list via the PERIODICLISTBASE register. Likewise, when the Periodic
Schedule Enable bit is a one, then the host controller does use the PERIODICLISTBASE register to
traverse the periodic schedule. The host controller will not react to modifications to the Periodic Schedule
Enable immediately. In order to eliminate conflicts with split transactions, the host controller evaluates the
Periodic Schedule Enable bit only when FRINDEX[2:0] is zero. The system software must not disable the
periodic schedule if the schedule contains an active split transaction work item that spans the 0b000
micro-frame. These work items must be removed from the schedule before the Periodic Schedule Enable
bit is cleared. The Periodic Schedule Status bit in the USBSTS register indicates status of the periodic
schedule. The system software enables (or disables) the periodic schedule by setting (or clearing) the
Periodic Schedule Enable bit in the USBCMD register. The software then can poll the Periodic Schedule
Status bit to determine when the periodic schedule has made the desired transition. The software must not
modify the Periodic Schedule Enable bit unless the value of the Periodic Schedule Enable bit equals that
of the Periodic Schedule Status bit.
The periodic schedule is used to manage all isochronous and interrupt transfer streams. The base of the
periodic schedule is the periodic frame list. The software links schedule data structures to the periodic
frame list to produce a graph of scheduled data structures. The graph represents an appropriate sequence
of transactions on the USB.
Figure 24-47 illustrates isochronous transfers (using iTDs and siTDs) with a
period of one are linked directly to the periodic frame list. Interrupt transfers (are managed with queue
heads) and isochronous streams with periods other than one are linked following the period-one
iTD/siTDs. Interrupt queue heads are linked into the frame list ordered by poll rate. Longer poll rates are
linked first (for example, closest to the periodic frame list), followed by shorter poll rates, with queue
heads with a poll rate of one, on the very end.
Table 24-64. Operation of FRINDEX and SOFV (SOF Value Register)
Current Next
FRINDEX[13:3] SOFV FRINDEX[2:0] FRINDEX[13:3] SOFV FRINDEX[2:0]
N N 111 N+1 N 000
N+1 N 000 N+1 N+1 001
N+1 N+1 001 N+1 N+1 010
N+1 N+1 010 N+1 N+1 011
N+1 N+1 011 N+1 N+1 100
N+1 N+1 100 N+1 N+1 101
N+1 N+1 101 N+1 N+1 110
N+1 N+1 110 N+1 N+1 111