NXP Semiconductors MCF5253, Reference Manual

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MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 10-1
Chapter 10
Chip Select Module
The Chip Select Module provides user-programmable control of the three chip select outputs, two buffer
enable outputs and one output-enable signal. This chapter describes the operation, memory map, and
register descriptions of the Chip Select module, including the chip select address, mask, and control
registers.
10.1 Chip Select Features
• Three programmable chip select outputs (CS0/CS4, CS1 and CS2 (IDE_DIOR and IDE_DIOW))
• IORDY and TA handshake pins
• Two programmable buffers enable signals for glueless interface to bus buffers
• Address masking for memory block sizes from 64 Kbytes to 4Gbytes
• Programmable wait states
• Port size is 16 bits
10.2 Chip Select Signals
The MCF5253 provides three programmable chip selects that can directly interface with SRAM, EPROM,
EEPROM, and peripherals. Chip select CS2 provides separate read and write strobes for an AT-bus
peripheral interface, and uses IORDY signalling to insert wait states.
10.2.1 CS0/CS4
CS0 is the first chip select and it addresses either the on-chip or external boot memory. At power-on reset,
all bus cycles are mapped to the CS0. This allows the boot memory to be defined at any address space.
CS0 is the only chip select initialized at reset.
During power-on reset, pin A23 is sensed. A resistor should be connected between this pin and VDD or
GND. Depending whether a pull-up or pull-down is mounted, different options are selected as described
in
Table 10-1 .
Table 10-1. CS0 Operation
Pin Description
A23 Pull-up: Boot from memory connected to CS0/CS4. CS0/CS4 function is CS0
Pull-down: Boot from on-chip boot ROM. CS0/CS4 function becomes CS4