NXP Semiconductors MCF5253, Reference Manual, Page: 155 / 648

System Integration Module (SIM)
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 9-11
9.4.2 Secondary Interrupt Controller Registers
The secondary controller serves 64 interrupt sources with programmable interrupt levels. All 64 interrupts
are auto-vectored. Interrupt pending registers and interrupt mask registers are decentralized, and available
in the modules that own the interrupts.
Address MBAR + 0x40 Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
QSPI DMA3 DMA2
W
Reset – – – – – – – – – – – – – – – –
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
DMA1 DMA0 UAR1 UAR0 I
2
C TIMER1 TIMER0 SWT
W
Reset – – – – – – – – – – – – – – – –
Figure 9-6. Interrupt Pending Register (IPR)
Table 9-10. Interrupt Pending Register (IPR) Field Descriptions
Field Description
31–19 Reserved.
18–8
IPR
Each Interrupt Pending bit corresponds to an interrupt source defined by the Interrupt Control Register. At every
clock this register samples the signal generated by the interrupting source. The corresponding bit in this register
reflects the state of the interrupt signal even if the corresponding mask bit were set. The IPR is a read-only longword
register.
0 The corresponding interrupt source does not have an interrupt pending
1 The corresponding interrupt source has an interrupt pending
7–0 Reserved, should be cleared.
Table 9-11. Secondary Interrupt Controller Registers Memory Map
Address Name Width Description Reset Value Access
MBAR2 + $140 INTPRI1 32 Interrupts 0–7 priority $00 R/W
MBAR2 + $144 INTPRI2 32 Interrupts 8–15 priority $00 R/W
MBAR2 + $148 INTPRI3 32 Interrupts 16–23 priority $00 R/W
MBAR2 + $14C INTPRI4 32 Interrupts 24–31 priority $00 R/W
MBAR2 + $150 INTPRI5 32 Interrupts 32–39 priority $00 R/W
MBAR2 + $154 INTPRI6 32 Interrupts 40–47 priority $00 R/W
MBAR2 + $158 INTPRI7 32 Interrupts 48–55 priority $00 R/W
MBAR2 + $15C INTPRI8 32 Interrupts 56–63 priority $00 R/W