NXP Semiconductors MCF5253, Reference Manual

Page: 489 / 648

Universal Serial Bus Interface
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 24-27
24.6.3.11 Transmit FIFO Tuning Controls Register (TXFILLTUNING)—Non-EHCI
This register is not defined in the EHCI specification. This register is used to control and dynamically
change the burst size used during data movement on DMA transfers. It is used only in host mode.
The fields in this register control performance tuning associated with how the module posts data to the TX
latency FIFO before moving the data onto the USB bus. The specific areas of performance include the how
much data to post into the FIFO and an estimate for how long that operation should take in the target
system.
Definitions:
T
0
= Standard packet overhead
T
1
= Time to send data payload
T
s
= Total Packet Flight Time (send-only) packet ( T
s
= T
0
+ T
1
)
T
ff
= Time to fetch packet into TX FIFO up to specified level.
T
p
= Total Packet Time (fetch and send) packet ( T
p
= T
ff
+ T
s
)
Upon discovery of a transmit (OUT/SETUP) packet in the data structures, host controller checks to ensure
T
p
remains before the end of the [micro]frame. If so it proceeds to pre-fill the TX FIFO. If at anytime
during the pre-fill operation the time remaining the [micro]frame is < T
s
then the packet attempt ceases and
the packet is tried at a later time. Although this is not an error condition and the module eventually
recovers, a mark is made in the scheduler health counter to note the occurrence of a back-off event. When
a back-off event is detected, the partial packet fetched may need to be discarded from the latency buffer to
make room for periodic traffic that will begin after the next SOF. Too many back-off events can waste
bandwidth and power on the system bus and thus should be minimized (not necessarily eliminated).
Back-offs can be minimized with use of the TSCHHEALTH (
T
ff
) parameter described below.
Table 24-24. Master Interface Data Burst Size (BURSTSIZE) Register Field Descriptions
Field Description
31–16 Reserved.
15–8
TXPBURST
Programable TX Burst Length. This register represents the maximum length of a burst in 32-bit words while
moving data from system memory to the USB bus. Must not be set to greater that 4.
7–0
RXPBURST
Programable RX Burst Length. This register represents the maximum length of a burst in 32-bit words while
moving data from the USB bus to system memory. Must not be set to greater than 4.