NXP Semiconductors MCF5253, Reference Manual, Page: 152 / 648

System Integration Module (SIM)
MCF5253 Reference Manual, Rev. 1
9-8 Freescale Semiconductor
Table 9-8 shows all possible primary source priority schemes for the MCF5253. The interrupt source in
this table can be any internal interrupt source programmed to the given level and priority. For example,
assume that two internal interrupt sources were programmed to IL[2:0] =110, one having a priority of
IP[1:0] = 01 and one having a priority of IP[1:0] = 10. If both assert an interrupt request at the same time,
the order of servicing would occur as follows:
1. Internal module with IL[2:0] =110 and IP[1:0] = 10 would be serviced first
2. Internal module with IL[2:0] = 110 and IP[1:0] = 01 would be serviced last
Address See Memory Map Table 9-5 Access: User read/write
7 6 5 4 3 2 1 0
R
AVEC IL[2] IL[1] IL[0] IP[1] IP[0]
W
Reset 0 – – 0 0 0 0 0
Figure 9-4. Interrupt Control Register (ICR)
Table 9-6. Interrupt Control Register (ICR) Field Descriptions
Field Description
7
AVEC
The Autovector Enable bit determines whether the interrupt-acknowledge cycle requires an autovector response (for
the internal interrupt level indicated in IL[2:0] for each interrupt).
0 Interrupting source returns vector during interrupt-acknowledge cycle
1 SIM generates auto vector during interrupt acknowledge cycle
6–5 Reserved.
4–2
IL
The Interrupt Level bits indicate the interrupt level assigned to each interrupt input.
1–0
IP
The Interrupt Priority bits indicate the interrupt priority within the interrupt level assignment.
Table 9-7
shows the
priority levels associated with the IP contents.
Table 9-7. Interrupt Priority Assignment
IP[1:0] Priority
00 Lower
01 Low
10 High
11 Higher
Table 9-8. Interrupt Priority Scheme
Interrupt Level
Internal Module ICR Reg
Interrupt Source
IL[2:0] IP[1] IP[0]
7 111 1 1 Internal Module
7 111 1 0 Internal Module