NXP Semiconductors MCF5253, Reference Manual

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Phase-Locked Loop and Clock Dividers
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 4-5
9. If field is “000”, divide by 8
10. Fvcxo min. 200 MHz max. is 400 MHz
11. This bit controls power-down.
12. Faudio is the audio clock. It is LRCK3/AUDIOCLK/GPIO43 when address pin A20/A24 is connected with a pull-up to Vdd, it
is CRIN or CRIN/2 when address pin A20/A24 is connected with a pull-down to GND.
4.2.1 PLL Operation
The input to the PLL is either CRIN, or CRIN divided by two. Selection is done by CRSEL. The PLL
divides this input frequency by a programmable division factor
(PLLDIV) . In the PLL phase/frequency
detector, this divided clock is compared with the VCXO output clock divided by (VCXODIV) . As a result,
Fvcxo = Fin
×
(2
×
VCXODIV) / (PLLDIV).
NOTE
The PLL lock counter is designed for worst case audio input frequency (Fin)
of 33.8688 MHz. This will result in the required 0.5 ms for the PLL to lock.
Other Fin frequencies can be used, however, the resulting lock time will be
slightly longer.
In a second step, this VCXO clock is divided by (VCXOOUT * CPUDIV) to create the CPU clock
PSTCLK.
The multiplexers that switch between PLL clock and CRIN is glitch-free, so no system reset is needed
when switching between bypass and PLL modes.
NOTE
It is important that before reprogramming the PLL division factors, users
must switch to PLL bypass mode. After reprogramming, users may
immediately switch back to PLL enabled mode. Switching back is delayed
internally until the PLL is locked.
4.2.2 PLL Lock-In Time
PLL lock time is typically around 10 ms.
4.2.3 PLL Electrical Limits
Due to implementation of the block, some limits apply to the PLL block. These limitations are shown in
Table 4-5 .
Table 4-5. PLL Electrical Limits
Name
Minimum
Frequency MHz
Maximum
Frequency MHz
Reason
Fvcxo 200 400 PLL limitations
Fcpu 0 140 Maximum operating frequency of device
Fin/PLLDIV 2 8 PLL limitations