NXP Semiconductors MCF5253, Reference Manual, Page: 181 / 648

Chip Select Module
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 10-5
10.4.2 Chip Select Module Registers
The various chip select registers in the module are described in this section.
10.4.2.1 Chip Select Address Register
The Chip Select Address registers (CSAR x ) determine the base address of the corresponding chip select
pin. These read/write registers are 32-bit in length.
MBAR + 0x8A CSCR0 16 Chip-Select Control Register–Bank 0 BSTR = BSTW = 0;
AA = 1; PS =;
WS3 = WS2 = WS1 = WS0 = 1
R/W
MBAR + 0x8C CSAR1 16 Chip-Select Address Register–Bank 1 Uninitialized R/W
MBAR + 0x90 CSMR1 32 Chip-Select Mask Register–Bank 1 Uninitialized
(except V = 0)
R/W
MBAR + 0x96 CSCR1 16 Chip-Select Control Register–Bank 1 Uninitialized R/W
MBAR + 0x98 CSAR2 16 Chip-Select Address Register–IDE Uninitialized R/W
MBAR + 0x9C CSMR2 32 Chip-Select Mask Register–IDE Uninitialized
(except V = 0)
R/W
MBAR + 0xA2 CSCR2 16 Chip-Select Control Register–IDE Uninitialized R/W
MBAR + 0xA4 CSAR3 16 Chip-Select Address Register–Bank 3 Uninitialized R/W
MBAR + 0xA8 CSMR3 32 Chip-Select Mask Register–Bank 3 Uninitialized
(except V = 0)
R/W
MBAR + 0xAE CSCR3 16 Chip-Select Control Register–Bank 3 Uninitialized R/W
MBAR + 0xB0 CSAR4 16 Chip-Select Address Register–Bank 4 Uninitialized R/W
MBAR + 0xB4 CSMR4 32 Chip-Select Mask Register–Bank 4 Uninitialized
(except V = 0)
R/W
MBAR + 0xBA CSCR4 16 Chip-Select Control Register–Bank 4 Uninitialized R/W
1
Addresses not assigned to a register and undefined register bits are reserved for future expansion. Write accesses to these
reserved address spaces and reserved register bits are undefined.
2
The reset value column indicates the register initial value at reset.
Table 10-2. Memory Map of Chip-Select Registers (continued)
Address
1
Name Width Description Reset
2
Access