NXP Semiconductors MCF5253, Reference Manual

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Background Debug Mode (BDM) Interface
MCF5253 Reference Manual, Rev. 1
20-38 Freescale Semiconductor
16
IPW
If set, the Inhibit Processor Writes to Debug Registers bit inhibits any processor-initiated writes to the debug
module’s programming model registers. This bit can only be modified by commands from the external
development system.
15
MAP
If set, the Force Processor References in Emulator Mode bit forces the processor to map all references while
in emulator mode to a special address space, TT = $2, TM = $5 or $6. If cleared, all emulator-mode references
are mapped into supervisor code and data spaces.
14
TRC
If set, the Force Emulation Mode on Trace Exception bit forces the processor to enter emulator mode when a
trace exception occurs.
13
EMU
If set, the Force Emulation Mode bit forces the processor to begin execution in emulator mode. Refer to
Section 20.4.1.1, “Emulator Mode.”
12–11
DDC
The 2-bit Debug Data Control field provides configuration control for capturing operand data for display on the
DDATA port. The encoding is:
00 No operand data is displayed
01 Capture all M-Bus write data
10 Capture all M-Bus read data
11 Capture all M-Bus read and write data
In all cases, the DDATA port displays the number of bytes defined by the operand reference size. For example,
byte displays 8 bits, word displays 16 bits, and long displays 32 bits (one nibble at a time across multiple clock
cycles.) Refer to
Section 20.2.1.7, “Begin Data Transfer (PST = $8–$B).”
10
UHE
The User Halt Enable bit selects the CPU privilege level required to execute the HALT instruction.
0 HALT is a privileged, supervisor-only instruction
1 HALT is a non-privileged, supervisor/user instruction
9–8
BTB
The 2-bit Branch Target Bytes field defines the number of bytes of branch target address to be displayed on
the DDATA outputs. The encoding is:
00 0 bytes
01 Lower two bytes of the target address
10 Lower three bytes of the target address
11 Entire four-byte target address
Refer to
Section 20.2.1.5, “Begin Execution of Taken Branch (PST = $5).”
6
NPL
If set, the Non-Pipelined Mode bit forces the processor core to operate in a nonpipeline mode of operation. In
this mode, the processor effectively executes a single instruction at a time with no overlap.
When operating in non-pipelined mode, performance is severely degraded. For the V3 design, operation in
this mode essentially adds 6 cycles to the execution time of each instruction. Given that the measured
Effective Cycles per Instruction for V3 is ~2 cycles/instruction, meaning performance in non-pipeline mode
would be ~8 cycles/instruction, or approximately 25% compared to the pipelined performance.
Regardless of the state of CSR[6], if a PC breakpoint is triggered, it is always reported before the instruction
with the breakpoint is executed. The occurrence of an address and/or data breakpoint trigger is imprecise in
normal pipeline operation. When operating in non-pipeline mode, these triggers are always reported before
the next instruction begins execution. In this mode, the trigger reporting can be considered to be precise.
As previously detailed, the occurrence of an address and/or data breakpoint should always happen before the
next instruction begins execution. Therefore the occurrence of the address/data breakpoints should be
guaranteed.
Table 20-22. Configuration/Status Register (CSR) Field Descriptions (continued)
Field Description