NXP Semiconductors MCF5253, Reference Manual, Page: 161 / 648

System Integration Module (SIM)
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 9-17
Notes:
1. INTMON1, INTMON2 registers are used to route an interrupt from the secondary interrupt controller ( Section 9.3, “SIM Module
Programming Registers ” ) such that the interrupt status can be monitored on either the external INTMON1 or INTMON2 pin.
This feature is intended to help measure the latency of an interrupt service routine.
2. Bits 7–4 of the register can be read to obtain the value of the software interrupts 0
–
3. When written zero, the value of the
corresponding software interrupt will not change. When written one, the corresponding software interrupt is set to a 1.
3. Bits 3–0 of the register can be read to read the value of software interrupts 0
–
3. When written zero, the value of the
corresponding software interrupt will not change. When written one, the corresponding software interrupt is set to 0.
4. To write SOFTINT_SET and SOFTINT_CLR registers, while avoiding writing to the INTMONx fields, use word-size or byte-size
addressing to update only bits 0–7.
9.5 System Protection and Reset Status Registers
This section provides the system Reset Status register and information about the Software Watchdog Timer
and associated registers and descriptions.
9.5.1 Reset Status Register
The RSR contains a bit for each reset source to the SIM. A bit set to 1 indicates the last type of reset that
occurred. The RSR is updated by the reset control logic on completion of the reset operation. Only one bit
will be set at any given time in the RSR. If a reset occurs and the user failed to clear this register, reset
control logic will clear all bits and set the appropriate bit to indicate the current cause of reset. The RSR
programming model is illustrated as follows.
The Reset Status Register (RSR) is an 8-bit supervisor read-write register.
9.5.2 Software Watchdog Timer
The Software Watchdog Timer (SWT) prevents system lockup if the software become trapped in loops
with no controlled exit.
Address MBAR + $00 Access: User read/write
7 6 5 4 3 2 1 0
R
HRST SWTR
W
Reset 1 0 0 0 0 0 0 0
Figure 9-9. Reset Status Register (RSR)
Table 9-17. Reset Status Register (RSR) Field Descriptions
Field Description
HRST For the Hardware or System Reset, a 1 = An external device driving RSTI caused the last reset. Assertion of reset
by an external device causes the core processor to take a reset exception. All registers in internal peripherals and
the SIM are reset.
SWTR For the Software Watchdog Timer Reset, a 1 = The last reset was caused by the software watchdog timer. If SWRI
in the SYPCR is set and the software watchdog timer times out, a hardware reset occurs.