NXP Semiconductors MCF5253, Reference Manual

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Instruction Cache
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 5-7
24
CINV
The Cache Invalidate bit forces the cache to invalidate each tag array entry. The invalidation process requires 32
machine cycles, with a single cache entry cleared per machine cycle. The state of this bit is always read as a zero.
After a hardware reset, the cache must be invalidated before it is enabled.
0 No operation
1 Invalidate all cache locations
23–11 Reserved, should be cleared.
10
CEIB
The Cache Enable Noncacheable Instruction Bursting bit enables the line-fill buffer to be loaded with burst transfers
under control of CLINF[1:0] for non-cacheable accesses. Noncacheable accesses are never written into the memory
array.
0 Disable burst fetches on noncacheable accesses
1 Enable burst fetches on noncacheable accesses
9
DCM
The Default Cache Mode bit defines the default cache mode: 0 is cacheable, 1 is noncacheable. For more
information on the selection of the effective memory attributes, see
Section 5.4.2, “Memory Reference Attributes.”
0 Default cacheable
1 Default noncacheable
8
DBWE
The Default Buffered Write Enable bit defines the default value for enabling buffered writes. If DBWE = 0, the
termination of an operand write cycle on the processor's local bus is delayed until the external bus cycle is
completed. If DBWE = 1, the write cycle on the local bus is terminated immediately and the operation buffered in
the bus controller. In this mode, operand write cycles are effectively decoupled between the processor's local bus
and the external bus.
Generally, enabled buffered writes provide higher system performance but recovery from access errors can be more
difficult. For the ColdFire CPU, reporting access errors on operand writes is always imprecise and enabling buffered
writes simply further decouples the write instruction from the signaling of the fault.
0 Disable buffered writes
1 Enable buffered writes
7 Reserved, should be cleared.
6
DWP
Default Write Protection
0 Read and write accesses permitted
1 Only read accesses permitted
5–2 Reserved, should be cleared.
1–0
CLNF
The Cache Line Fill bits control the size of the memory request the cache issues to the bus controller for different
initial line access offsets.
Table 5-5 shows the fetch size.
Table 5-5. External Fetch Size Based on Miss Address and CLNF
CLNF[1:0]
Longword Address Bits
00 01 10 11
00 Line Line Line Longword
01 Line Line Longword Longword
10 Line Line Line Line
11 Line Line Line Line
Table 5-4. Cache Control Register Field Descriptions (continued)
Bit Name Description