NXP Semiconductors MCF5253, Reference Manual

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Bus Operation
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 8-15
Figure 8-16. Master Reset Timing
During the master reset period, the data bus is being tri-stated, the address bus is driven to any value, and
all other bus signals are driven to their negated state. Once RSTI negates, the bus stays in this state until
the core begins the first bus cycle for reset exception processing. A master reset causes any bus cycle
(including DRAM refresh cycle) to terminate. In addition, master reset initializes registers appropriately
for a reset exception.
If at power-on reset, the MCF5253 is configured to boot from external memory connected to CS0. Then
CS0 is configured to address the external boot ROM / Flash. The configuration for CS0 at this time is
hard-wired inside the MCF5253.
Configuration is summarized in Table 8-9 .
8.7.1 Software Watchdog Reset
The software watchdog reset is performed anytime the executing software does not provide the correct
write sequence with the enable-control bit set. This reset helps recovery from runaway software or
nonterminated bus cycles. During the software watchdog reset period all signals are driven either to a high
impedance state or a negated state as appropriate.
Table 8-9. Power-On Reset Configuration for CS0
Port Size 16 Bits
Cycle type Internal termination, 15 wait cycles
Burst inhibit asserted for both read and write cycles
VDD
RSTI
CRIN
D[31:16]
SDRAS , SDCAS
CS, OE
>16
CLKIN CYCLES
SDWE , BCLKE
A[23:1], RW