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Universal Serial Bus Interface
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor
24-55
24.8.4.4
siTD Buffer Pointer List (Plus)
DWords 4 and 5 are the data buffer page pointers for the transfer. This structure supports one physical page
cross. The most significant 20 bits of each DWord in this section are the 4K (page) aligned buffer pointers.
The least significant 12 bits of each DWord are used as additional transfer state.
7–0
Status
This field records the status of the transaction executed by the host controller for this slot. This field
is a bit vector with the following encoding:
Status Bit
Definition
7
Active. Set by the software to enable the execution of an isochronous split
transaction by the Host Controller.
6
ERR. Set by the Host Controller when an ERR response is received from the
Companion Controller.
5
Data Buffer Error. Set by the Host Controller during status update to indicate that the
Host Controller is unable to keep up with the reception of incoming data (overrun) or
is unable to supply data fast enough during transmission (under run). In the case of
an under run, the Host Controller will transmit an incorrect CRC (thus invalidating the
data at the endpoint). If an overrun condition occurs, no action is necessary.
4
Babble Detected. Set by the Host Controller during status update when” babble” is
detected during the transaction generated by this descriptor.
3
Transaction Error (XactErr). Set by the Host Controller during status update in the
case where the host did not receive a valid response from the device (Time-out,
CRC, Bad PID, etc.). This bit will only be set for IN transactions.
2
Missed Micro-Frame. The host controller detected that a host-induced hold- off
caused the host controller to miss a required complete-split transaction.
1
Split Transaction State (SplitXstate). The bit encodings are:
0 Do Start Split. This value directs the host controller to issue a Start split
transaction to the endpoint when a match is encountered in the S-mask.
1 Do Complete Split. This value directs the host controller to issue a Complete split
transaction to the endpoint when a match is encountered in the C-mask.
0
Reserved. Bit reserved for future use and should be cleared.
Table 24-48. siTD Buffer Pointer Page 0 (Plus)
Bit
Name
Description
31–12 Buffer
Pointer
(Page 0)
Bits [31–12] is a 4K page-aligned, physical memory addresses. These bits correspond to physical
address bits [31–12] respectively. The field P specifies the current active pointer
11–0
Current Offset
The 12 least significant bits of the Page 0 pointer is the current byte offset for the current page
pointer (as selected with the page indicator bit (P field)). The host controller is not required to write
this field back when the siTD is retired (Active bit transitioned from a one to a zero).
Table 24-47. siTD Transfer Status and Control (continued)
Bit
Name
Description
Summary of Contents for MCF5253
Page 1: ...Document Number MCF5253RM Rev 1 08 2008 MCF5253 Reference Manual...
Page 26: ...MCF5253 Reference Manual Rev 1 xxvi Freescale Semiconductor...
Page 32: ...MCF5253 Reference Manual Rev 1 xxxii Freescale Semiconductor...
Page 46: ...MCF5253 Introduction MCF5253 Reference Manual Rev 1 1 14 Freescale Semiconductor...
Page 62: ...Signal Description MCF5253 Reference Manual Rev 1 2 16 Freescale Semiconductor...
Page 98: ...Instruction Cache MCF5253 Reference Manual Rev 1 5 10 Freescale Semiconductor...
Page 104: ...Static RAM SRAM MCF5253 Reference Manual Rev 1 6 6 Freescale Semiconductor...
Page 128: ...Synchronous DRAM Controller Module MCF5253 Reference Manual Rev 1 7 24 Freescale Semiconductor...
Page 144: ...Bus Operation MCF5253 Reference Manual Rev 1 8 16 Freescale Semiconductor...
Page 176: ...System Integration Module SIM MCF5253 Reference Manual Rev 1 9 32 Freescale Semiconductor...
Page 198: ...Analog to Digital Converter ADC MCF5253 Reference Manual Rev 1 12 6 Freescale Semiconductor...
Page 246: ...DMA Controller MCF5253 Reference Manual Rev 1 14 18 Freescale Semiconductor...
Page 282: ...UART Modules MCF5253 Reference Manual Rev 1 15 36 Freescale Semiconductor...
Page 344: ...Audio Interface Module AIM MCF5253 Reference Manual Rev 1 17 46 Freescale Semiconductor...
Page 362: ...I2 C Modules MCF5253 Reference Manual Rev 1 18 18 Freescale Semiconductor...
Page 370: ...Boot ROM MCF5253 Reference Manual Rev 1 19 8 Freescale Semiconductor...