NXP Semiconductors MCF5253, Reference Manual, Page: 236 / 648

DMA Controller
MCF5253 Reference Manual, Rev. 1
14-8 Freescale Semiconductor
The DONE bit in the DMA status register ( Table 14-9 ) is set when the entire block transfer is complete.
When a transfer sequence is initiated and the BCR contains a value that is not divisible by 16, 4, or 2 when
the DMA is configured for line, longword, or word transfers, respectively, the configuration error bit (CE)
in the DMA status register (DSR) is set and the transfer does not take place. Refer to
Section 14.4.6, “DMA
Status Register,” for more details.
14.4.5 DMA Control Register
The DMA control register (DCR) sets the configuration of the DMA controller module. Depending on the
state of the BCR24BIT in the MPARK register in the SIM module, the DMA control register looks slightly
different. Specifically, the AT bit (DCR[15]) is included when BCR24BIT = 1, providing greater flexibility
in DMA transfer acknowledge.
Address MBAR + $30C
MBAR + $34C
MBAR + $38C
MBAR + $3CC
Access: User read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R
BCR15 BCR14 BCR13 BCR12 BCR11 BCR10 BCR9 BCR8 BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0
W
Reset – – – – – – – – – – – – – – – –
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
W
Reset – – – – – – – – – – – – – – – –
Figure 14-7. Byte Count Register (BCR)—BCR24BIT = 0