NXP Semiconductors MCF5253, Reference Manual, Page: 163 / 648

System Integration Module (SIM)
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 9-19
Both writes must occur in the order listed prior to the SWT timeout, but any number of instructions or
accesses to the SWSR can be executed between the two writes. This allows interrupts and exceptions to
occur, if necessary, between the two writes.
Caution should be exercised when changing system protection control register (SYPCR) values after the
software watchdog timer (SWT) has been enabled with the setting of the SWE register bit, because it is
difficult to determine the state of the SWT while the timer is running. The SWP and SWT[1:0] bits in
SYPCR determine the SWT timeout period. The countdown value determined by the SWP and SWT[1:0]
bits is constantly compared with that specified by these bits. Therefore, altering the contents of the SWP
and SWT[1:0] bits improperly will result in unpredictable processor behavior. The following steps must
be taken in order to change one of these values in the SYPCR:
1. Disable SWT by writing a 0 to the SWE bit in SYPCR.
2. Service the SWSR, write $55, then write $AA to SWSR. This action resets the counter.
3. Re-write new SWT[1:0] and SWP values to SYPCR register.
4. Re-enable SWT by writing a 1 to SWE bit in SYPCR. Users can perform this task in Step 3.
9.5.2.1 System Protection Control Register
The SYPCR controls the software watchdog timer, timeout periods, and software watchdog timer transfer
acknowledge.
The SYPCR is an 8-bit read-write register. The register can be read at any time, but can be written only if
SWT IRQ is not pending. At system reset, the software watchdog timer is disabled.
Address MBAR + $01 Access: User read/write
7 6 5 4 3 2 1 0
R
SWE SWRI SWP SWT[1] SWT[0] SWTA SWTAVAL
W
Reset 0 0 0 0 0 0 0 –
Figure 9-11. System Protection Control Register (SYPCR)
Table 9-18. System Protection Control Register (SYPCR) Field Descriptions
Field Description
7
SWE
Software Watchdog Enable
0 SWT disabled.
1 SWT enabled.
6
SWRI
Software Watchdog Reset/Interrupt Select
0 If SWT timeout occurs, SWT generates an interrupt to the core processor at the level programmed into the IL
bits of ICR0.
1 SWT causes soft reset to be asserted for all modules of the part.
5
SWP
Software Watchdog Prescalar
0 SWT clock not prescaled.
1 SWT clock prescaled by a value of 8192.