NXP Semiconductors MCF5253, Reference Manual, Page: 399 / 648

Background Debug Mode (BDM) Interface
MCF5253 Reference Manual, Rev. 1
Freescale Semiconductor 20-29
20.4.1.2 Debug Module Hardware
20.4.1.2.1 Reuse of Debug Module Hardware (Rev. A)
The debug module implementation provides a common hardware structure for both BDM and breakpoint
functionality. Several structures are used for both BDM and breakpoint purposes.
Table 20-18 identifies
the shared hardware structures.
The shared use of these hardware structures means the loading of the register to perform any specified
function is destructive to the shared function. For example, if an operand address breakpoint is loaded into
the debug module, a BDM command to access memory overwrites the breakpoint. If a data breakpoint is
configured, a BDM write command overwrites the breakpoint contents.
20.5 Debug Module Memory Map and Register Definitions
In addition to the existing BDM commands that provide access to the processor’s registers and the memory
subsystem, the debug module contains nine registers to support the required functionality. All of these
registers are treated as 32-bit quantities, regardless of the actual number of bits in the implementation. The
registers, known as the debug control registers, are accessed through the BDM port using two new BDM
commands: WDMREG and RDMREG. These commands contain a 4-bit field, DRc, which specifies the
particular register being accessed.
These registers are also accessible from the processor’s supervisor programming model through the
execution of the WDEBUG instruction. Thus, the breakpoint hardware within the debug module may be
accessed by the external development system using the serial interface, or by the operating system running
on the processor core. It is the responsibility of the software to guarantee that all accesses to these resources
are serialized and logically consistent. The hardware provides a locking mechanism in the CSR to allow
the external development system to disable any attempted writes by the processor to the breakpoint
registers (setting IPW = 1). The BDM commands must not be issued if the ColdFire processor is accessing
the debug module registers using the WDEBUG instruction.
Table 20-18. Shared BDM/Breakpoint Hardware
Register BDM Function Breakpoint Function
AATR Bus Attributes for All Memory Commands Attributes for Address Breakpoint
ABHR Address for All Memory Commands Address for Address Breakpoint
DBR Data for All BDM Write Commands Data for Data Breakpoint