CHAPTER 5.0 Functional Overview
5-38
CDS7324 (FORMERLY LSF-0819)
Rev. A
INSTALLATION & USER’S MANUAL
5.11.2 Velocity Loop compensator
In velocity mode, the velocity compensator is an I-PI configuration, and has the structure as shown below: -
velf
iqdv
Kp
Ki
Kie
1
s
1
s
+
+
+
-
-
imax
-imax
vcmdsav
motvelliminc
-motvelliminc
+
+
Anti-windup
Anti-windup
Figure 5.8 : Velocity Loop (When in velocity mode) Compensator Structure
The output of this compensator is limited to
±
imax
, and these limit’s can be read using the upper and lower limit
parameters of the compensator. The I-PI velocity loop compensator has gains as listed below.
Field
Number
Name Type
Units
1317
velocity_mode_p-gain
f32
Nm/rad/s
1318
velocity_mode _i-gain
f32
Nm/rad
1319
velocity_mode _ie-gain
f32
none
Table 5.28 List of Velocity Loop Compensator Gains
Field
Number
Name Type
Units
1320
velocity_mode _error
f32
incs/Tsamp
1165
velocity_filtered
f32
incs/Tsamp
1120
current_demand_velocity_comp_output
f32
Amps.
Table 5.29 List of Velocity Loop Read-only Parameters
5.11.2.1
Velocity Loop Sample Rate
The velocity loop sample period can be set to any multiple of the current loop sample period (~100us) using the
parameter
velocity_loop_rate_divider
(1136).
