Appendix D – GTXI Buffer Board
163
IRQ Channels
The available IRQ channels in PC-AT are 3,4,5,6,7,9,10,11,12,14,
and 15. These channels can be assigned to GTXI by writing to the
IMR register in the GTXI buffer.
IRQ Mask Register (IMR)
Internal address (IA) is 6.
Bit #
15-11
10-0
Function U IQE10-IQE0
Table D-12: IRQ Mask Register Bit Functions
U
Unused
IQE
IRQ channel enable. ‘0’ – IRQ disabled. ‘1’ – IRQ
enabled. See table below for bit assignments.
The default value for bits 15-0 is 0000h (all disabled).
The following table describes IRQ channels and their corresponding
bits in the DMR register:
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