Hitachi H8S/2645, Hardware Manual

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15.2.6 Transmit Wait Cancel Register (TXCR)
The transmit wait cancel register (TXCR) is a 16-bit readable/writable register that controls
cancellation of transmit wait messages in mailboxes (buffers).
TXCR
Bit: 15 14 13 12 11 10 9 8
TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 —
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W —
Bit: 7 6 5 4 3 2 1 0
TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bits 15 to 9 and 7 to 0—Transmit Wait Cancel Register: These bits control cancellation of
transmit wait messages in the corresponding HCAN mailboxes.
Bit x: TXCRx Description
0 Transmit message cancellation idle state in corresponding mailbox
(Initial value)
[Clearing condition]
Completion of TXPR clearing (when transmit message is canceled normally)
1 TXPR cleared for corresponding mailbox (transmit message cancellation)
(x = 15 to 0)
Bit 8—Reserved: This bit always reads 0. The write value should always be 0.