Hitachi H8S/2645 Hardware Manual Download Page 20

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6.2.3

Break Control Register A (BCRA) ....................................................................... 132

6.2.4

Break Control Register B (BCRB) ....................................................................... 134

6.2.5

Module Stop Control Register C (MSTPCRC) .................................................... 134

6.3

Operation............................................................................................................................ 135
6.3.1

PC Break Interrupt Due to Instruction Fetch ........................................................ 135

6.3.2

PC Break Interrupt Due to Data Access ............................................................... 135

6.3.3

Notes on PC Break Interrupt Handling................................................................. 136

6.3.4

Operation in Transitions to Power-Down Modes ................................................. 136

6.3.5

PC Break Operation in Continuous Data Transfer ............................................... 137

6.3.6

When Instruction Execution is Delayed by One State.......................................... 138

6.3.7

Additional Notes ................................................................................................... 139

Section 7

Bus Controller..................................................................................141

7.1

Overview............................................................................................................................ 141
7.1.1

Features ................................................................................................................. 141

7.1.2

Block Diagram...................................................................................................... 142

7.1.3

Pin Configuration.................................................................................................. 143

7.1.4

7.2

Register Descriptions ......................................................................................................... 144
7.2.1

Bus Width Control Register (ABWCR) ............................................................... 144

7.2.2

Access State Control Register (ASTCR).............................................................. 144

7.2.3

Wait Control Registers H and L (WCRH, WCRL) .............................................. 146

7.2.4

Bus Control Register H (BCRH) .......................................................................... 150

7.2.5

Bus Control Register L (BCRL) ........................................................................... 151

7.2.6

Pin Function Control Register (PFCR) ................................................................. 152

7.3

Overview of Bus Control ................................................................................................... 154
7.3.1

Area Partitioning................................................................................................... 154

7.3.2

Bus Specifications ................................................................................................ 155

7.3.3

Memory Interfaces................................................................................................ 156

7.3.4

Interface Specifications for Each Area ................................................................. 157

7.4

Basic Bus Interface ............................................................................................................ 158
7.4.1

Overview............................................................................................................... 158

7.4.2

Data Size and Data Alignment.............................................................................. 158

7.4.3

Valid Strobes ........................................................................................................ 160

7.4.4

Basic Timing......................................................................................................... 161

7.4.5

Wait Control.......................................................................................................... 169

7.5

Burst ROM Interface.......................................................................................................... 171
7.5.1

Overview............................................................................................................... 171

7.5.2

Basic Timing......................................................................................................... 171

7.5.3

Wait Control.......................................................................................................... 173

7.6

Idle Cycle ........................................................................................................................... 174
7.6.1

Operation .............................................................................................................. 174

7.6.2

Pin States During Idle Cycles ............................................................................... 177

Summary of Contents for H8S/2645

Page 1: ...Chip Microcomputer H8S 2646 Series H8S 2646 HD6432646 H8S 2645 HD6432645 H8S 2647 HD6432647 H8S 2648 HD6432648 H8S 2646R F ZTAT HD64F2646R H8S 2648R F ZTAT HD64F2648R Hardware Manual ADE 602 207C Rev 4 0 9 20 02 Hitachi Ltd ...

Page 2: ...of bodily injury such as aerospace aeronautics nuclear power combustion control transportation traffic safety equipment or medical equipment for life support 4 Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating operating supply voltage range heat radiation characteristics installation conditions and other characteristics Hita...

Page 3: ...te When power is first supplied the product s state is undefined The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin During the period where the states are undefined the register settings and the output state of each pin are also undefined Design your system so that it does not malfunction because of processing wh...

Page 4: ......

Page 5: ...2646 Series in the design of application systems Members of this audience are expected to understand the fundamentals of electrical circuits logical circuits and microcomputers Objective This manual was written to explain the hardware functions and electrical characteristics of the H8S 2646 Series to the above audience Refer to the H8S 2600 Series H8S 2000 Series Programming Manual for a detailed ...

Page 6: ...g Manual ADE 602 083 Users manuals for development tools Manual Title ADE No C C Complier Assembler Optimized Linkage Editor User s Manual ADE 702 247 Simulator Debugger for Windows Users Manual ADE 702 037 Hitachi Embedded Workshop Users Manual ADE 702 201 Application Notes Manual Title ADE No H8S Series Technical Q A ADE 502 059 ...

Page 7: ...s located in on chip ROM normal mode is set and data is transferred from the on chip ROM to an internal I O register the time required for the DTC operation is 14 states The time from activation to the end of the data write is 11 states 9 4 2 Register Configuration Table 9 6 Port 3 Register Configuration 242 Name Abbreviation R W Initial Value Address Port 3 data direction register P3DDR W H 00 H ...

Page 8: ...nd TSEG2 in BCR Moved to Bit Rate and Bit Timing Settings in section 15 3 2 Initialization after Hardware Reset 15 2 11 Interrupt Register IRR 547 Bit 15 Overload Frame Interrupt Flag Status flag indicating that the HCAN has transmitted an overload frame Bit 15 IRR7 Description 0 Clearing condition Writing 1 Initial value 1 Overload frame transmission Setting conditions When overload frame is tran...

Page 9: ...5 3 for the range of values that can be used as settings TSEG1 TSEG2 BRP sample point and SJW for BCR Table 15 3 BCR Register Value Setting Ranges Name Abbreviation Min Value Max Value Time segment 1 TSEG1 B 0011 B 1111 Time segment 2 TSEG2 B 001 B 111 Baud rate prescaler BRP B 000000 B 111111 Sample point SAM B 0 B 1 Re synchronization jump width SJW B 00 B 11 Value Setting Ranges The value of SJ...

Page 10: ...hronization is established Note The time quanta values of TSEG1 and TSEG2 become the value of TSEG 1 Figure 15 6 Detailed Description of Timing within 1 Bit HCAN bit rate calculation fCLK 2 BRP 1 3 TSEG1 TSEG2 Bit rate Note fCLK ø system clock The BCR values are used for BRP TSEG1 and TSEG2 BCR Setting Constraints TSEG1 TSEG2 SJW SJW 0 to 3 These constraints allow the setting range shown in table ...

Page 11: ... 1 When a transition is made to the HCAN sleep mode by means of the above steps a 10 cycle wait should be inserted after the TxPR setting After an HCAN sleep mode transition release the HCAN sleep mode by clearing MCR5 to 0 11 Message transmission cancellation TxCR If all the following conditions are met when cancellation of a transmission message is performed by means of TxCR of the HCAN the TxCR...

Page 12: ...VCC 0 7 VCC 0 3 V EXTAL VCC 0 7 VCC 0 3 Ports 1 to 3 5 H J K Ports PF0 PF3 PF7 2 2 VCC 0 3 HRxD 2 2 VCC 0 3 Ports A to E Ports PF2 PF4 to PF6 2 2 LPVCC 0 3 Ports 4 9 AVCC 0 7 AVCC 0 3 Input low voltage RES STBY NMI FWE MD2 to MD0 VIL 0 3 0 5 V EXTAL 0 3 0 8 Ports 1 to 3 5 A to F H J K 0 3 0 8 HRxD 0 3 VCC 0 2 Notes amended 1 If the A D converter is not used do not leave the AVCC Vref and AVSS pins...

Page 13: ... 0 R W 13 ABACK5 0 R W 12 ABACK4 0 R W 11 ABACK3 0 R W 8 0 10 ABACK2 0 R W 9 ABACK1 0 R W 7 ABACK15 0 R W 6 ABACK14 0 R W 5 ABACK13 0 R W 4 ABACK12 0 R W 3 ABACK11 0 R W 0 ABACK8 0 R W 2 ABACK10 0 R W 1 ABACK9 0 R W Bit Initial value Read Write Bit Initial value Read Write Note added Note Only 1 can be written to clear the flag RXPR Receive Complete Register H F80E HCAN 15 RXPR7 0 R W 14 RXPR6 0 R...

Page 14: ... Initial value Read Write Note added Note Only 1 can be written to clear the flag 885 886 IRR Interrupt Register H F812 HCAN 15 IRR7 0 R W 14 IRR6 0 R W 13 IRR5 0 R W 12 IRR4 0 R W 11 IRR3 0 R W 8 IRR0 1 R W 10 IRR2 0 R W 9 IRR1 0 R W Bit Initial value Read Write 0 Clearing condition Writing 1 1 Overload frame transmission Setting conditions When overload frame is transmitted Overload Frame Interr...

Page 15: ...ite Bit Initial value Read Write Unread Message Status Flags 0 Clearing condition Writing 1 x 15 to 0 1 Unread receive message is overwritten by a new message Setting condition When a new message is received before RXPR is cleared Note added Note Only 1 can be written to clear the flag 1009 PFDR Port F Data Register H FF0E Port 7 0 R W 6 PF6DR 0 R W 5 PF5DR 0 R W 4 PF4DR 0 R W 3 PF3DR 0 R W 0 PF0D...

Page 16: ......

Page 17: ...erview 36 2 4 2 General Registers 37 2 4 3 Control Registers 38 2 4 4 Initial Register Values 40 2 5 Data Formats 41 2 5 1 General Register Data Formats 41 2 5 2 Memory Data Formats 43 2 6 Instruction Set 44 2 6 1 Overview 44 2 6 2 Instructions and Addressing Modes 45 2 6 3 Table of Instructions Classified by Function 47 2 6 4 Basic Instruction Formats 56 2 7 Addressing Modes and Effective Address...

Page 18: ... System Control Register SYSCR 81 3 2 3 Pin Function Control Register PFCR 82 3 3 Operating Mode Descriptions 84 3 3 1 Mode 4 84 3 3 2 Mode 5 84 3 3 3 Mode 6 84 3 3 4 Mode 7 84 3 4 Pin Functions in Each Operating Mode 85 3 5 Address Map in Each Operating Mode 85 Section 4 Exception Handling 89 4 1 Overview 89 4 1 1 Exception Handling Types and Priority 89 4 1 2 Exception Handling Operation 90 4 1 ...

Page 19: ...1 Interrupt Control Modes and Interrupt Operation 114 5 4 2 Interrupt Control Mode 0 117 5 4 3 Interrupt Control Mode 2 119 5 4 4 Interrupt Exception Handling Sequence 121 5 4 5 Interrupt Response Times 122 5 5 Usage Notes 123 5 5 1 Contention between Interrupt Generation and Disabling 123 5 5 2 Instructions that Disable Interrupts 124 5 5 3 Times when Interrupts are Disabled 124 5 5 4 Interrupts ...

Page 20: ...7 1 4 Register Configuration 143 7 2 Register Descriptions 144 7 2 1 Bus Width Control Register ABWCR 144 7 2 2 Access State Control Register ASTCR 144 7 2 3 Wait Control Registers H and L WCRH WCRL 146 7 2 4 Bus Control Register H BCRH 150 7 2 5 Bus Control Register L BCRL 151 7 2 6 Pin Function Control Register PFCR 152 7 3 Overview of Bus Control 154 7 3 1 Area Partitioning 154 7 3 2 Bus Specif...

Page 21: ...ter A CRA 187 8 2 6 DTC Transfer Count Register B CRB 188 8 2 7 DTC Enable Registers DTCER 188 8 2 8 DTC Vector Register DTVECR 189 8 2 9 Module Stop Control Register A MSTPCRA 190 8 3 Operation 192 8 3 1 Overview 192 8 3 2 Activation Sources 194 8 3 3 DTC Vector Table 195 8 3 4 Location of Register Information in Address Space 199 8 3 5 Normal Mode 200 8 3 6 Repeat Mode 201 8 3 7 Block Transfer M...

Page 22: ...w 253 9 7 2 Register Configuration 254 9 7 3 Pin Functions 254 9 8 Port A 255 9 8 1 Overview 255 9 8 2 Register Configuration 256 9 8 3 Pin Functions 258 9 8 4 MOS Input Pull Up Function 260 9 9 Port B 261 9 9 1 Overview 261 9 9 2 Register Configuration 262 9 9 3 Pin Functions 264 9 9 4 MOS Input Pull Up Function 265 9 10 Port C 266 9 10 1 Overview 266 9 10 2 Register Configuration 267 9 10 3 Pin ...

Page 23: ... TPU 295 10 1 Overview 295 10 1 1 Features 295 10 1 2 Block Diagram 299 10 1 3 Pin Configuration 300 10 1 4 Register Configuration 302 10 2 Register Descriptions 304 10 2 1 Timer Control Register TCR 304 10 2 2 Timer Mode Register TMDR 309 10 2 3 Timer I O Control Register TIOR 311 10 2 4 Timer Interrupt Enable Register TIER 324 10 2 5 Timer Status Register TSR 327 10 2 6 Timer Counter TCNT 331 10...

Page 24: ...gister Descriptions 391 11 2 1 Next Data Enable Registers H and L NDERH NDERL 391 11 2 2 Output Data Registers H and L PODRH PODRL 392 11 2 3 Next Data Registers H and L NDRH NDRL 393 11 2 4 Notes on NDR Access 393 11 2 5 PPG Output Control Register PCR 395 11 2 6 PPG Output Mode Register PMR 397 11 2 7 Port 1 Data Direction Register P1DDR 400 11 2 8 Module Stop Control Register A MSTPCRA 400 11 3...

Page 25: ...tchdog Timer Mode 430 12 5 5 OVF Flag Clearing in Interval Timer Mode 430 Section 13 Serial Communication Interface SCI 431 13 1 Overview 431 13 1 1 Features 431 13 1 2 Block Diagram 433 13 1 3 Pin Configuration 434 13 1 4 Register Configuration 435 13 2 Register Descriptions 436 13 2 1 Receive Shift Register RSR 436 13 2 2 Receive Data Register RDR 436 13 2 3 Transmit Shift Register TSR 437 13 2 ...

Page 26: ... Notes 527 Section 15 Hitachi Controller Area Network HCAN 531 15 1 Overview 531 15 1 1 Features 531 15 1 2 Block Diagram 532 15 1 3 Pin Configuration 533 15 1 4 Register Configuration 533 15 2 Register Descriptions 535 15 2 1 Master Control Register MCR 535 15 2 2 General Status Register GSR 536 15 2 3 Bit Configuration Register BCR 538 15 2 4 Mailbox Configuration Register MBCR 540 15 2 5 Transm...

Page 27: ... 15 5 Usage Notes 585 Section 16 A D Converter 587 16 1 Overview 587 16 1 1 Features 587 16 1 2 Block Diagram 588 16 1 3 Pin Configuration 589 16 1 4 Register Configuration 590 16 2 Register Descriptions 591 16 2 1 A D Data Registers A to D ADDRA to ADDRD 591 16 2 2 A D Control Status Register ADCSR 592 16 2 3 A D Control Register ADCR 595 16 2 4 Module Stop Control Register A MSTPCRA 596 16 3 Int...

Page 28: ...gisters 626 17 3 2 8 Bit Data Registers 626 17 4 Operation 627 17 4 1 PWM Channel 1 Operation 627 17 4 2 PWM Channel 2 Operation 628 17 5 Usage Note 629 Section 18 LCD Controller Driver 631 18 1 Overview 631 18 1 1 Features 631 18 1 2 Block Diagram 632 18 1 3 Pin Configuration 633 18 1 4 Register Configuration 633 18 2 Register Descriptions 634 18 2 1 LCD Port Control Register LPCR 634 18 2 2 LCD ...

Page 29: ...Emulation Register RAMER 671 20 5 6 Flash Memory Power Control Register FLPWCR 672 20 6 On Board Programming Modes 673 20 6 1 Boot Mode 673 20 6 2 User Program Mode 678 20 7 Flash Memory Programming Erasing 680 20 7 1 Program Mode 682 20 7 2 Program Verify Mode 683 20 7 3 Erase Mode 687 20 7 4 Erase Verify Mode 687 20 8 Protection 689 20 8 1 Hardware Protection 689 20 8 2 Software Protection 690 2...

Page 30: ...ator 722 21 8 Subclock Waveform Generation Circuit 723 21 9 Note on Crystal Resonator 723 Section 22 Power Down Modes 725 22 1 Overview 725 22 1 1 Register Configuration 729 22 2 Register Descriptions 730 22 2 1 Standby Control Register SBYCR 730 22 2 2 System Clock Control Register SCKCR 732 22 2 3 Low Power Control Register LPWRCR 733 22 2 4 Timer Control Status Register TCSR 736 22 2 5 Module S...

Page 31: ...23 Electrical Characteristics 753 23 1 Absolute Maximum Ratings 753 23 2 Power Supply Voltage and Operating Frequency Range 754 23 3 DC Characteristics 755 23 4 AC Characteristics 760 23 4 1 Clock Timing 761 23 4 2 Control Signal Timing 763 23 4 3 Bus Timing 765 23 4 4 Timing of On Chip Supporting Modules 771 23 5 A D Conversion Characteristics 776 23 6 LCD Characteristics 777 23 7 Flash Memory Ch...

Page 32: ...Block Diagram 1096 C 8 Port B Block Diagram 1097 C 9 Port C Block Diagram 1098 C 10 Port D Block Diagram 1099 C 11 Port E Block Diagram 1100 C 12 Port F Block Diagrams 1101 C 13 Port G Block Diagram 1108 C 14 Port J Block Diagram 1109 C 15 Port K Block Diagram 1110 Appendix D Pin States 1111 D 1 Port States in Each Mode 1111 Appendix E Timing of Transition to and Recovery from Hardware Standby Mod...

Page 33: ...eral functions required for system configuration include data transfer controller DTC bus masters ROM and RAM memory a 16 bit timer pulse unit TPU programmable pulse generator PPG watchdog timer WDT serial communication interface SCI Hitachi controller area network HCAN A D converter motor control PWM timer PWM LCD controller driver LCDC and I O ports On chip ROM is available as 128 kbyte flash me...

Page 34: ...dress space divided into 8 areas with bus specifications settable independently for each area Choice of 8 bit or 16 bit access space for each area 2 state or 3 state access space can be designated for each area Number of program wait states can be set for each area Direct connection to burst ROM supported PC break controller Supports debugging functions by means of PC break interrupts Two break ch...

Page 35: ...olution 10 bits Input 12 channels High speed conversion 13 3 µs minimum conversion time at 20 MHz operation Single or scan mode selectable Sample and hold circuit A D conversion can be activated by external trigger or timer trigger Motor control PWM timer PWM Maximum of 16 10 bit PWM outputs Eight outputs with two channels each built in Duty settable between 0 and 100 Automatic transfer of buffer ...

Page 36: ...ode Sleep mode Module stop mode Software standby mode Hardware standby mode Sub clock operation Operating modes Four MCU operating modes CPU External Data Bus Mode Operating Mode Description On Chip ROM Initial Value Maximum Value 4 Advanced On chip ROM disabled expansion mode Disabled 16 bits 16 bits 5 On chip ROM disabled expansion mode Disabled 8 bits 16 bits 6 On chip ROM enabled expansion mod...

Page 37: ...Name Mask ROM Version F ZTAT Version ROM RAM Bytes Packages HD6432646 HD64F2646R 128 k 4 k FP 144J HD6432645 64 k 2 k FP 144G HD6432648 HD64F2648R 128 k 4 k FP 144J HD6432647 64 k 2 k FP 144G The HD64F2646R and HD64F2648R use an FP 144J package ...

Page 38: ...3 TIOCB1 TCLKC P16 PO14 TIOCA2 IRQ1 P17 PO15 TIOCB2 TCLKD P20 TIOCA3 P21 TIOCB3 P22 TIOCC3 P23 TIOCD3 P24 TIOCA4 P25 TIOCB4 P26 TIOCA5 P27 TIOCB5 P52 P51 P50 PK7 PK6 PF7 ø PF6 AS SEG20 PF5 RD SEG19 PF4 HWR SEG18 PF3 LWR ADTRG IRQ3 PF2 WAIT SEG17 PF0 IRQ2 RAM TPU HCAN PPG MD2 MD1 MD0 OSC2 OSC1 EXTAL XTAL PLLCAP PLLVSS STBY RES NMI FWE 2 HTxD HRxD H8S 2600 CPU DTC PH0 PWM1A PH1 PWM1B PH2 PWM1C PH3 P...

Page 39: ...3 TIOCB1 TCLKC P16 PO14 TIOCA2 IRQ1 P17 PO15 TIOCB2 TCLKD P20 TIOCA3 P21 TIOCB3 P22 TIOCC3 P23 TIOCD3 P24 TIOCA4 P25 TIOCB4 P26 TIOCA5 P27 TIOCB5 P52 SCK2 P51 RxD2 P50 TxD2 PK7 PK6 PF7 ø PF6 AS SEG36 PF5 RD SEG35 PF4 HWR SEG34 PF3 LWR ADTRG IRQ3 PF2 WAIT SEG33 PF0 IRQ2 RAM TPU HCAN PPG MD2 MD1 MD0 OSC2 OSC1 EXTAL XTAL PLLCAP PLLVSS STBY RES NMI FWE 2 HTxD HRxD H8S 2600 CPU DTC PH0 PWM1A PH1 PWM1B ...

Page 40: ...31 RXD0 P30 TXD0 MD0 MD1 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 MD2 PWMVSS PJ7 PWM2H PJ6 PWM2G PJ5 PWM2F PJ4 PWM2E PWMVCC PJ3 PWM2D PJ2 PWM2C PJ1 PWM2B PJ0 PWM2A PWMVSS PH7 PWM1H PH6 PWM1G PH5 PWM1F PH4 PWM1E PWMVC...

Page 41: ...101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 MD2 PWMVSS PJ7 PWM2H PJ6 PWM2G PJ5 PWM2F PJ4 PWM2E PWMVCC PJ3 PWM2D PJ2 PWM2C PJ1 PWM2B PJ0 PWM2A PWMVSS PH7 PWM1H PH6 PWM1G PH5 PWM1F PH4 PWM1E PWMVCC PH3 PWM1D PH2 PWM1C PH1 PWM1B PH0 PWM1A PWMVSS PA3 ...

Page 42: ...E1 6 PE2 D2 PE2 D2 PE2 D2 PE2 7 PE3 D3 PE3 D3 PE3 D3 PE3 8 PE4 D4 PE4 D4 PE4 D4 PE4 9 PE5 D5 PE5 D5 PE5 D5 PE5 10 PE6 D6 PE6 D6 PE6 D6 PE6 11 PE7 D7 PE7 D7 PE7 D7 PE7 12 Vss Vss Vss Vss 13 D8 D8 D8 PD0 14 D9 D9 D9 PD1 15 D10 D10 D10 PD2 16 D11 D11 D11 PD3 17 D12 D12 D12 PD4 18 D13 D13 D13 PD5 19 D14 D14 D14 PD6 20 D15 D15 D15 PD7 21 LPVcc LPVcc LPVcc LPVcc 22 A0 A0 PC0 A0 SEG1 PC0 SEG1 23 A1 A1 PC...

Page 43: ...EG19 PF5 SEG19 42 AS SEG20 AS SEG20 AS SEG20 PF6 SEG20 43 PA4 A20 SEG21 PA4 A20 SEG21 PA4 A20 SEG21 PA4 SEG21 44 PA5 A21 SEG22 PA5 A21 SEG22 PA5 A21 SEG22 PA5 SEG22 45 PA6 A22 SEG23 PA6 A22 SEG23 PA6 A22 SEG23 PA6 SEG23 46 PA7 A23 SEG24 PA7 A23 SEG24 PA7 A23 SEG24 PA7 SEG24 47 PA0 A16 COM1 PA0 A16 COM1 PA0 A16 COM1 PA0 COM1 48 PA1 A17 COM2 PA1 A17 COM2 PA1 A17 COM2 PA1 COM2 49 PA2 A18 COM3 PA2 A18...

Page 44: ...WM2H PJ7 PWM2H 71 PWMVss PWMVss PWMVss PWMVss 72 MD2 MD2 MD2 MD2 73 MD1 MD1 MD1 MD1 74 MD0 MD0 MD0 MD0 75 P30 TxD0 P30 TxD0 P30 TxD0 P30 TxD0 76 P31 RxD0 P31 RxD0 P31 RxD0 P31 RxD0 77 P32 SCK0 IRQ4 P32 SCK0 IRQ4 P32 SCK0 IRQ4 P32 SCK0 IRQ4 78 P33 TxD1 P33 TxD1 P33 TxD1 P33 TxD1 79 P34 RxD1 P34 RxD1 P34 RxD1 P34 RxD1 80 P35 SCK1 IRQ5 P35 SCK1 IRQ5 P35 SCK1 IRQ5 P35 SCK1 IRQ5 81 P36 P36 P36 P36 82 P...

Page 45: ...O11 TIOCD0 TCLKB 105 P14 PO12 TIOCA1 IRQ0 P14 PO12 TIOCA1 IRQ0 P14 PO12 TIOCA1 IRQ0 P14 PO12 TIOCA1 IRQ0 106 P15 PO13 TIOCB1 TCLKC P15 PO13 TIOCB1 TCLKC P15 PO13 TIOCB1 TCLKC P15 PO13 TIOCB1 TCLKC 107 P16 PO14 TIOCA2 IRQ1 P16 PO14 TIOCA2 IRQ1 P16 PO14 TIOCA2 IRQ1 P16 PO14 TIOCA2 IRQ1 108 P17 PO15 TIOCB2 TCLKD P17 PO15 TIOCB2 TCLKD P17 PO15 TIOCB2 TCLKD P17 PO15 TIOCB2 TCLKD 109 HTxD HTxD HTxD HTxD...

Page 46: ...3 AN3 P43 AN3 132 P44 AN4 P44 AN4 P44 AN4 P44 AN4 133 P45 AN5 P45 AN5 P45 AN5 P45 AN5 134 P46 AN6 P46 AN6 P46 AN6 P46 AN6 135 P47 AN7 P47 AN7 P47 AN7 P47 AN7 136 P90 AN8 P90 AN8 P90 AN8 P90 AN8 137 P91 AN9 P91 AN9 P91 AN9 P91 AN9 138 P92 AN10 P92 AN10 P92 AN10 P92 AN10 139 P93 AN11 P93 AN11 P93 AN11 P93 AN11 140 P94 P94 P94 P94 141 P95 P95 P95 P95 142 P96 P96 P96 P96 143 P97 P97 P97 P97 144 AVss A...

Page 47: ...SEG6 PE5 D5 SEG6 PE5 D5 SEG6 PE5 SEG6 10 PE6 D6 SEG7 PE6 D6 SEG7 PE6 D6 SEG7 PE6 SEG7 11 PE7 D7 SEG8 PE7 D7 SEG8 PE7 D7 SEG8 PE7 SEG8 12 Vss Vss Vss Vss 13 D8 D8 D8 SEG9 PD0 SEG9 14 D9 D9 D9 SEG10 PD1 SEG10 15 D10 D10 D10 SEG11 PD2 SEG11 16 D11 D11 D11 SEG12 PD3 SEG12 17 D12 D12 D12 SEG13 PD4 SEG13 18 D13 D13 D13 SEG14 PD5 SEG14 19 D14 D14 D14 SEG15 PD6 SEG15 20 D15 D15 D15 SEG16 PD7 SEG16 21 LPVc...

Page 48: ...35 PF5 SEG35 42 AS SEG36 AS SEG36 AS SEG36 PF6 SEG36 43 PA4 A20 SEG37 PA4 A20 SEG37 PA4 A20 SEG37 PA4 SEG37 44 PA5 A21 SEG38 PA5 A21 SEG38 PA5 A21 SEG38 PA5 SEG38 45 PA6 A22 SEG39 PA6 A22 SEG39 PA6 A22 SEG39 PA6 SEG39 46 PA7 A23 SEG40 PA7 A23 SEG40 PA7 A23 SEG40 PA7 SEG40 47 PA0 A16 COM1 PA0 A16 COM1 PA0 A16 COM1 PA0 COM1 48 PA1 A17 COM2 PA1 A17 COM2 PA1 A17 COM2 PA1 COM2 49 PA2 A18 COM3 PA2 A18 C...

Page 49: ...WM2H PJ7 PWM2H 71 PWMVss PWMVss PWMVss PWMVss 72 MD2 MD2 MD2 MD2 73 MD1 MD1 MD1 MD1 74 MD0 MD0 MD0 MD0 75 P30 TxD0 P30 TxD0 P30 TxD0 P30 TxD0 76 P31 RxD0 P31 RxD0 P31 RxD0 P31 RxD0 77 P32 SCK0 IRQ4 P32 SCK0 IRQ4 P32 SCK0 IRQ4 P32 SCK0 IRQ4 78 P33 TxD1 P33 TxD1 P33 TxD1 P33 TxD1 79 P34 RxD1 P34 RxD1 P34 RxD1 P34 RxD1 80 P35 SCK1 IRQ5 P35 SCK1 IRQ5 P35 SCK1 IRQ5 P35 SCK1 IRQ5 81 P36 P36 P36 P36 82 P...

Page 50: ...TIOCA1 IRQ0 P14 PO12 TIOCA1 IRQ0 P14 PO12 TIOCA1 IRQ0 P14 PO12 TIOCA1 IRQ0 106 P15 PO13 TIOCB1 TCLKC P15 PO13 TIOCB1 TCLKC P15 PO13 TIOCB1 TCLKC P15 PO13 TIOCB1 TCLKC 107 P16 PO14 TIOCA2 IRQ1 P16 PO14 TIOCA2 IRQ1 P16 PO14 TIOCA2 IRQ1 P16 PO14 TIOCA2 IRQ1 108 P17 PO15 TIOCB2 TCLKD P17 PO15 TIOCB2 TCLKD P17 PO15 TIOCB2 TCLKD P17 PO15 TIOCB2 TCLKD 109 HTxD HTxD HTxD HTxD 110 HRxD HRxD HRxD HRxD 111 P...

Page 51: ...3 AN3 P43 AN3 132 P44 AN4 P44 AN4 P44 AN4 P44 AN4 133 P45 AN5 P45 AN5 P45 AN5 P45 AN5 134 P46 AN6 P46 AN6 P46 AN6 P46 AN6 135 P47 AN7 P47 AN7 P47 AN7 P47 AN7 136 P90 AN8 P90 AN8 P90 AN8 P90 AN8 137 P91 AN9 P91 AN9 P91 AN9 P91 AN9 138 P92 AN10 P92 AN10 P92 AN10 P92 AN10 139 P93 AN11 P93 AN11 P93 AN11 P93 AN11 140 P94 P94 P94 P94 141 P95 P95 P95 P95 142 P96 P96 P96 P96 143 P97 P97 P97 P97 144 AVss A...

Page 52: ... port J and the motor control PWM timer output Connect all pins to the system power supply 0 V VCL Input On chip step down power supply pin Pin for connecting the on chip step down power supply to a capacitor for voltage stabilization Connect to Vss via a 0 1 µF capacitor which should be located near the pin Do not connect this pin to an external power supply Clock PLLVss Input PLL ground Ground f...

Page 53: ...rol RES Input Reset input When this pin is driven low the chip is reset STBY Input Standby When this pin is driven low a transition is made to hardware standby mode FWE Input Flash write enable Pin for flash memory use in planning stage Interrupts NMI Input Nonmaskable interrupt Requests a nonmaskable interrupt When this pin is not used it should be fixed high IRQ5 to IRQ0 Input Interrupt request ...

Page 54: ...utput compare output or PWM output pins TIOCA1 TIOCB1 I O Input capture output compare match A1 and B1 The TGR1A and TGR1B input capture input or output compare output or PWM output pins TIOCA2 TIOCB2 I O Input capture output compare match A2 and B2 The TGR2A and TGR2B input capture input or output compare output or PWM output pins TIOCA3 TIOCB3 TIOCC3 TIOCD3 I O Input capture output compare match...

Page 55: ...sion HRxD Input HCAN receive data Pin for CAN bus reception A D converter AN11 to AN0 Input Analog 11 to 0 Analog input pins ADTRG Input A D conversion external trigger input Pin for input of an external trigger to start A D conversion AVcc Input Analog power supply A D converter power supply pin If the A D converter is not used connect this pin to the system power supply 5 V AVss Input Analog gro...

Page 56: ...put Port 4 8 bit input pins P52 to P50 I O Port 5 3 bit I O pins Input or output can be designated for each bit by means of the port 5 data direction register P5DDR P97 to P90 Input Port 9 8 bit input pins PA7 to PA0 I O Port A 8 bit I O pins Input or output can be designated for each bit by means of the port A data direction register PADDR PB7 to PB0 I O Port B 8 bit I O pins Input or output can ...

Page 57: ... I O Port H 8 bit I O pins Input or output can be designated for each bit by means of the port H data direction register PHDDR PJ7 to PJ0 I O Port J 8 bit I O pins Input or output can be designated for each bit by means of the port J data direction register PJDDR PK6 to PK7 I O Port K 2 bit I O pins Input or output can be designated for each bit by means of the port K data direction register PKDDR...

Page 58: ...26 ...

Page 59: ...ister architecture Sixteen 16 bit general registers also usable as sixteen 8 bit registers or eight 32 bit registers Sixty nine basic instructions 8 16 32 bit arithmetic and logic instructions Multiply and divide instructions Powerful bit manipulation instructions Multiply and accumulate instruction Eight addressing modes Register direct Rn Register indirect ERn Register indirect with displacement...

Page 60: ...to power down state by SLEEP instruction CPU clock speed selection 2 1 2 Differences between H8S 2600 CPU and H8S 2000 CPU The differences between the H8S 2600 CPU and the H8S 2000 CPU are as shown below Register configuration The MAC register is supported only by the H8S 2600 CPU Basic instructions The four instructions MAC CLRMAC LDMAC and STMAC are supported only by the H8S 2600 CPU Number of e...

Page 61: ...een enhanced to make effective use of the 16 Mbyte address space Enhanced instructions Addressing modes of bit manipulation instructions have been enhanced Signed multiply and divide instructions have been added A multiply and accumulate instruction has been added Two bit shift instructions have been added Instructions for saving and restoring multiple registers have been added A test and set inst...

Page 62: ... 2646 Series Normal mode Advanced mode Maximum 64 kbytes program and data areas combined Maximum 16 Mbytes for program and data areas combined Figure 2 1 CPU Operating Modes 1 Normal Mode Not Available in the H8S 2646 Series The exception vector table and stack have the same structure as in the H8 300 CPU Address Space A maximum address space of 64 kbytes can be accessed Extended Registers En The ...

Page 63: ...ndling H 0000 H 0001 H 0002 H 0003 H 0004 H 0005 H 0006 H 0007 H 0008 H 0009 H 000A H 000B Reset exception vector Exception vector 1 Exception vector 2 Exception vector table Reserved for system use Figure 2 2 Exception Vector Table Normal Mode The memory indirect addressing mode aa 8 employed in the JMP and JSR instructions uses an 8 bit absolute address included in the instruction code to specif...

Page 64: ...PC 16 bits SP SP Notes 1 2 3 When EXR is not used it is not stored on the stack SP when EXR is not used Ignored when returning SP 2 Figure 2 3 Stack Structure in Normal Mode 2 Advanced Mode Address Space Linear access is provided to a 16 Mbyte maximum address space architecturally a maximum 16 Mbyte program area and a maximum 4 Gbyte data area with a maximum of 4 Gbytes for program and data areas ...

Page 65: ...ctor Reserved for system use Reserved Exception vector 1 Reserved H 00000010 H 00000008 H 00000007 Figure 2 4 Exception Vector Table Advanced Mode The memory indirect addressing mode aa 8 employed in the JMP and JSR instructions uses an 8 bit absolute address included in the instruction code to specify a memory operand that contains a branch address In advanced mode the operand is a 32 bit longwor...

Page 66: ...exception handling they are stored as shown in figure 2 5 When EXR is invalid it is not pushed onto the stack For details see section 4 Exception Handling a Subroutine Branch b Exception Handling PC 24 bits EXR 1 Reserved 1 3 CCR PC 24 bits SP SP Notes 1 2 3 When EXR is not used it is not stored on the stack SP when EXR is not used Ignored when returning SP 2 Reserved Figure 2 5 Stack Structure in...

Page 67: ...mum 64 kbyte address space in normal mode and a maximum 16 Mbyte architecturally 4 Gbyte address space in advanced mode b Advanced Mode H 0000 H FFFF H 00000000 H FFFFFFFF H 00FFFFFF a Normal Mode Data area Program area Cannot be used by the H8S 2646 Series Note Not available in the H8S 2646 Series Figure 2 6 Memory Map ...

Page 68: ...ters En Control Registers CR Legend Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition code register Interrupt mask bit User bit or interrupt mask bit SP PC EXR T I2 to I0 CCR I UI Note Cannot be used as an interrupt mask bit in the H8S 2646 Series ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 SP I UI H U N Z V C CCR 7 6 5 4 3 2 1 0 Sign extension 63 32 41 0 31 MAC M...

Page 69: ... to R7 These registers are functionally equivalent providing a maximum sixteen 16 bit registers The E registers E0 to E7 are also referred to as extended registers The R registers divide into 8 bit general registers designated by the letters RH R0H to R7H and RL R0L to R7L These registers are functionally equivalent providing a maximum sixteen 8 bit registers Figure 2 8 illustrates the usage of th...

Page 70: ...ter PC This 24 bit counter indicates the address of the next instruction the CPU will execute The length of all CPU instructions is 2 bytes one word so the least significant PC bit is ignored When an instruction is fetched the least significant PC bit is regarded as 0 2 Extended Control Register EXR This 8 bit register contains the trace bit T and three interrupt mask bits I2 to I0 Bit 7 Trace Bit...

Page 71: ... 5 Interrupt Controller Bit 5 Half Carry Flag H When the ADD B ADDX B SUB B SUBX B CMP B or NEG B instruction is executed this flag is set to 1 if there is a carry or borrow at bit 3 and cleared to 0 otherwise When the ADD W SUB W CMP W or NEG W instruction is executed the H flag is set to 1 if there is a carry or borrow at bit 11 and cleared to 0 otherwise When the ADD L SUB L CMP L or NEG L inst...

Page 72: ...the results of multiply and accumulate operations It consists of two 32 bit registers denoted MACH and MACL The lower 10 bits of MACH are valid the upper bits are a sign extension 2 4 4 Initial Register Values Reset exception handling loads the CPU s program counter PC from the vector table clears the trace bit in EXR to 0 and sets the interrupt mask bits in CCR and EXR to 1 The other CCR bits and...

Page 73: ...s two digits of 4 bit BCD data 2 5 1 General Register Data Formats Figure 2 10 shows the data formats in general registers 7 6 5 4 3 2 1 0 Don t care 7 0 Don t care 7 6 5 4 3 2 1 0 4 3 7 0 7 0 Don t care Upper Lower LSB MSB LSB Data Type Register Number Data Format 1 bit data 1 bit data 4 bit BCD data 4 bit BCD data Byte data Byte data RnH RnL RnH RnL RnH RnL MSB Don t care Upper Lower 4 3 7 0 Don...

Page 74: ...gister ER General register E General register R General register RH General register RL Most significant bit Least significant bit Legend ERn En Rn RnH RnL MSB LSB 0 MSB LSB 15 Longword data ERn Data Type Register Number Data Format Figure 2 10 General Register Data Formats cont ...

Page 75: ...st significant bit of the address is regarded as 0 so the access starts at the preceding address This also applies to instruction fetches 7 6 5 4 3 2 1 0 7 0 MSB LSB MSB LSB MSB LSB Data Type Data Format 1 bit data Byte data Word data Longword data Address Address L Address L Address 2M Address 2M 1 Address 2N Address 2N 1 Address 2N 2 Address 2N 3 Figure 2 11 Memory Data Formats When ER7 is used ...

Page 76: ...D OR XOR NOT BWL 4 Shift SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR BWL 8 Bit manipulation BSET BCLR BNOT BTST BLD BILD BST BIST BAND BIAND BOR BIOR BXOR BIXOR B 14 Branch Bcc 2 JMP BSR JSR RTS 5 System control TRAPA RTE SLEEP LDC STC ANDC ORC XORC NOP 9 Block data transfer EEPMOV 1 Total 69 Notes B byte size W word size L longword size 1 POP W Rn and PUSH W Rn are identical to MOV W SP Rn and MOV ...

Page 77: ...ng Modes Addressing Modes Function Data transfer Arithmetic operations Instruction MOV BWL BWL BWL BWL BWL BWL B BWL BWL POP PUSH WL LDM STM L ADD CMP BWL BWL SUB WL BWL ADDX SUBX B B ADDS SUBS L INC DEC BWL DAA DAS B NEG BWL EXTU EXTS WL TAS 2 B MAC CLRMAC MOVFPE 1 B MOVTPE 1 MULXU BW DIVXU MULXS BW DIVXS LDMAC L STMAC xx Rn ERn d 16 ERn d 32 ERn ERn ERn aa 8 aa 16 aa 24 aa 32 d 8 PC d 16 PC aa 8...

Page 78: ... ORC XORC Bcc BSR JMP JSR RTS TRAPA RTE SLEEP LDC B B W W W W W W STC B W W W W W W NOT BWL BWL B B B B B NOP BW Legend B Byte W Word L Longword Notes 1 Not available in the H8S 2646 Series 2 Only register ER0 ER1 ER4 or ER5 should be used when using the TAS instruction xx Rn ERn d 16 ERn d 32 ERn ERn ERn aa 8 aa 16 aa 24 aa 32 d 8 PC d 16 PC aa 8 ...

Page 79: ...Ad Destination operand EAs Source operand EXR Extended control register CCR Condition code register N N negative flag in CCR Z Z zero flag in CCR V V overflow flag in CCR C C carry flag in CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT logical complement 8 16 24 32 8 16 2...

Page 80: ...d in the H8S 2646 Series MOVTPE B Cannot be used in the H8S 2646 Series POP W L SP Rn Pops a register from the stack POP W Rn is identical to MOV W SP Rn POP L ERn is identical to MOV L SP ERn PUSH W L Rn SP Pushes a register onto the stack PUSH W Rn is identical to MOV W Rn SP PUSH L ERn is identical to MOV L ERn SP LDM L SP Rn register list Pops two or more general registers from the stack STM L...

Page 81: ... operands can be incremented or decremented by 1 only ADDS SUBS L Rd 1 Rd Rd 2 Rd Rd 4 Rd Adds or subtracts the value 1 2 or 4 to or from data in a 32 bit register DAA DAS B Rd decimal adjust Rd Decimal adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4 bit BCD data MULXU B W Rd Rs Rd Performs unsigned multiplication on data in two general register...

Page 82: ... size or the lower 16 bits of a 32 bit register to longword size by padding with zeros on the left EXTS W L Rd sign extension Rd Extends the lower 8 bits of a 16 bit register to word size or the lower 16 bits of a 32 bit register to longword size by extending the sign bit TAS B ERd 0 1 bit 7 of ERd 2 Tests memory contents and sets the most significant bit bit 7 to 1 MAC EAs EAd MAC MAC Performs si...

Page 83: ...egister and another general register or immediate data NOT B W L Rd Rd Takes the one s complement of general register contents Shift operations SHAL SHAR B W L Rd shift Rd Performs an arithmetic shift on general register contents 1 bit or 2 bit shift is possible SHLL SHLR B W L Rd shift Rd Performs a logical shift on general register contents 1 bit or 2 bit shift is possible ROTL ROTR B W L Rd rot...

Page 84: ...general register or memory operand and sets or clears the Z flag accordingly The bit number is specified by 3 bit immediate data or the lower three bits of a general register BAND BIAND B B C bit No of EAd C ANDs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag C bit No of EAd C ANDs the carry flag with the inverse of a specified b...

Page 85: ...is specified by 3 bit immediate data BLD BILD B B bit No of EAd C Transfers a specified bit in a general register or memory operand to the carry flag bit No of EAd C Transfers the inverse of a specified bit in a general register or memory operand to the carry flag The bit number is specified by 3 bit immediate data BST BIST B B C bit No of EAd Transfers the carry flag value to a specified bit in a...

Page 86: ... Low or same C Z 1 BCC BHS Carry clear high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal Z 1 BVC Overflow clear V 0 BVS Overflow set V 1 BPL Plus N 0 BMI Minus N 1 BGE Greater or equal N V 0 BLT Less than N V 1 BGT Greater than Z N V 0 BLE Less or equal Z N V 1 JMP Branches unconditionally to a specified address BSR Branches to a subroutine at a specified address JSR Branches ...

Page 87: ...n them and memory The upper 8 bits are valid STC B W CCR EAd EXR EAd Transfers CCR or EXR contents to a general register or memory Although CCR and EXR are 8 bit registers word size transfers are performed between them and memory The upper 8 bits are valid ANDC B CCR IMM CCR EXR IMM EXR Logically ANDs the CCR or EXR contents with immediate data ORC B CCR IMM CCR EXR IMM EXR Logically ORs the CCR o...

Page 88: ...n Formats The CPU instructions consist of 2 byte 1 word units An instruction consists of an operation field op field a register field r field an effective address extension EA field and a condition field cc 1 Operation Field Indicates the function of the instruction the addressing mode and the operation to be carried out on the operand The operation field always includes the first four bits of the...

Page 89: ...V B d 16 Rn Rm etc 1 Operation field only 2 Operation field and register fields 3 Operation field register fields and effective address extension rn rm op EA disp 4 Operation field effective address extension and condition field op cc EA disp BRA d 16 etc Figure 2 12 Instruction Formats Examples ...

Page 90: ...rect with pre decrement ERn ERn 5 Absolute address aa 8 aa 16 aa 24 aa 32 6 Immediate xx 8 xx 16 xx 32 7 Program counter relative d 8 PC d 16 PC 8 Memory indirect aa 8 1 Register Direct Rn The register field of the instruction specifies an 8 16 or 32 bit general register containing the operand R0H to R7H and R0L to R7L can be specified as 8 bit registers R0 to R7 and E0 to E7 can be specified as 1...

Page 91: ...n For word or longword transfer instruction the register value should be even 5 Absolute Address aa 8 aa 16 aa 24 or aa 32 The instruction code contains the absolute address of a memory operand The absolute address may be 8 bits long aa 8 16 bits long aa 16 24 bits long aa 24 or 32 bits long aa 32 To access data the absolute address should be 8 bits aa 8 16 bits aa 16 or 32 bits aa 32 long For an ...

Page 92: ...added is the address of the first byte of the next instruction so the possible branching range is 126 to 128 bytes 63 to 64 words or 32766 to 32768 bytes 16383 to 16384 words from the branch instruction The resulting value should be an even number 8 Memory Indirect aa 8 This mode can be used by the JMP and JSR instructions The instruction code contains an 8 bit absolute address specifying a memory...

Page 93: ...nch address the least significant bit is regarded as 0 causing data to be accessed or instruction code to be fetched at the address preceding the specified address For further information see section 2 5 2 Memory Data Formats 2 7 2 Effective Address Calculation Table 2 6 indicates how effective addresses are calculated in each addressing mode In normal mode the upper 8 bits of the effective addres...

Page 94: ...eral register contents Register indirect ERn 2 Register indirect with displacement d 16 ERn or d 32 ERn 3 Register indirect with pre decrement ERn 4 General register contents General register contents Sign extension disp General register contents 1 2 or 4 General register contents 1 2 or 4 Byte Word Longword 1 2 4 Operand Size Value added 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 op r r op op r...

Page 95: ...8 7 Operand is immediate data No Addressing Mode and Instruction Format Effective Address Calculation Effective Address EA aa 24 31 0 16 15 31 0 24 23 31 0 op abs op abs abs op op abs op IMM H FFFF Don t care 24 23 Don t care 24 23 Don t care 24 23 Don t care Sign extension ...

Page 96: ...Instruction Format Effective Address Calculation Effective Address EA 23 23 31 8 7 0 15 0 31 8 7 0 disp H 000000 abs H 000000 31 0 24 23 31 0 16 15 31 0 24 23 op disp op abs op abs Sign extension PC contents abs Memory contents Memory contents H 00 Don t care 24 23 Don t care Don t care Note Not available in the H8S 2646 Series ...

Page 97: ...ransient state in which the CPU changes the normal processing flow in response to a reset interrupt or trap instruction Program execution state The CPU executes program instructions in sequence Bus released state The external bus has been released in response to a bus request signal from a bus master other than the CPU Power down state CPU operation is stopped to conserve power Sleep mode Software...

Page 98: ...er RES goes low A transition can also be made to the reset state when the watchdog timer overflows From any state a transition to hardware standby mode occurs when STBY goes low Apart from these states there are also the watch mode subactive mode and the subsleep mode See section 22 Power Down Modes E n d o f e x c e p t i o n h a n d l i n g Figure 2 15 State Transitions 2 8 2 Reset State When th...

Page 99: ... clock Exception handling starts immediately after a low to high transition at the RES pin or when the watchdog timer overflows Trace End of instruction execution or end of exception handling sequence 1 When the trace T bit is set to 1 the trace starts at the end of the current instruction or current exception handling sequence Interrupt End of instruction execution or end of exception handling se...

Page 100: ...is cleared to 0 and trace mode is cleared Interrupt masks are not affected The T bit saved on the stack retains its value of 1 and when the RTE instruction is executed to return from the trace exception handling routine trace mode is entered again Trace exception handling is not executed at the end of the RTE instruction Trace mode is not entered in interrupt control mode 0 regardless of the state...

Page 101: ...P EXR Reserved 1 a Interrupt control mode 0 b Interrupt control mode 2 CCR CCR 1 PC 16 bits SP CCR CCR 1 PC 16 bits SP EXR Reserved 1 Normal mode 2 Advanced mode Notes 1 Ignored when returning 2 Not available in the H8S 2646 Series Figure 2 16 Stack Structure after Exception Handling Examples ...

Page 102: ...subsleep mode and watch mode are power down states using subclock input For details refer to section 22 Power Down Modes 1 Sleep Mode A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit SSBY in the standby control register SBYCR is cleared to 0 In sleep mode CPU operations stop immediately after execution of the SLEEP instruction The contents of C...

Page 103: ...on chip supporting modules and the external address space 2 9 2 On Chip Memory ROM RAM On chip memory is accessed in one state The data bus is 16 bits wide permitting both byte and word transfer instruction Figure 2 17 shows the on chip memory access cycle Figure 2 18 shows the pin states Internal address bus Internal read signal Internal data bus Internal write signal Internal data bus ø Bus cycl...

Page 104: ...72 Bus cycle T1 Held Address bus AS RD HWR LWR Data bus ø High High High High impedance state Figure 2 18 Pin States during On Chip Memory Access ...

Page 105: ...articular internal I O register being accessed Figure 2 19 shows the access cycle for the on chip supporting modules Figure 2 20 shows the pin states Bus cycle T1 T2 Address Read data Write data Internal read signal Internal data bus Internal write signal Internal data bus Read access Write access Internal address bus ø Figure 2 19 On Chip Supporting Module Access Cycle ...

Page 106: ...74 Bus cycle T1 T2 Held Address bus AS RD HWR LWR Data bus ø High High High High impedance state Figure 2 20 Pin States during On Chip Supporting Module Access ...

Page 107: ...he pin states in figure 2 23 Internal address bus HCAN read signal Internal data bus HCAN write signal Internal data bus ø Bus cycle T1 Address Read Write Read data Write data T3 T2 T4 Figure 2 21 On Chip HCAN Module Access Cycle No Wait State Internal address bus HCAN read signal Internal data bus HCAN write signal Internal data bus ø Bus cycle T1 Address Read Write T3 T2 Tw Read data Write data ...

Page 108: ...10 1 TAS Instruction Only register ER0 ER1 ER4 or ER5 should be used when using the TAS instruction The TAS instruction is not generated by the Hitachi H8S and H8 300 series C C compilers If the TAS instruction is used as a user defined intrinsic function ensure that only register ER0 ER1 ER4 or ER5 is used 2 10 2 Caution to observe when using bit manipulation instructions The BSET BCLR BNOT BST a...

Page 109: ...be used to clear the flag of an internal I O register to 0 In that case if it is clearly known that the pertinent flag is set to 1 in an interrupt processing routine or other processing there is no need to read the flag in advance ...

Page 110: ...78 ...

Page 111: ...ded mode 8 bits 16 bits 6 1 0 On chip ROM enabled expanded mode Enabled 8 bits 16 bits 7 1 Single chip mode Note Not available in the H8S 2646 Series The CPU s architecture allows for 4 Gbytes of address space but the H8S 2646 Series actually accesses a maximum of 16 Mbytes Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices The external expansion...

Page 112: ...unction control register PFCR R W H 0D H 00 H FDEB Note Lower 16 bits of the address 3 2 Register Descriptions 3 2 1 Mode Control Register MDCR 7 1 6 0 5 0 4 0 3 0 0 MDS0 R 2 MDS2 R 1 MDS1 R Note Determined by pins MD2 to MD0 Bit Initial value R W MDCR is an 8 bit read only register that indicates the current operating mode of the H8S 2646 Series Bit 7 Reserved Cannot be written to Bits 6 to 3 Res...

Page 113: ... MACS Selects either saturating or non saturating calculation for the MAC instruction Bit 7 MACS Description 0 Non saturating calculation for MAC instruction Initial value 1 Saturating calculation for MAC instruction Bit 6 Reserved This bit is always read as 0 and cannot be modified Bits 5 and 4 Interrupt Control Mode 1 and 0 INTM1 INTM0 These bits select the control mode of the interrupt controll...

Page 114: ...DTC is used the RAME bit must not be cleared to 0 3 2 3 Pin Function Control Register PFCR 7 0 R W 6 0 R W 5 0 R W 4 0 R W 3 AE3 1 0 R W 0 AE0 1 0 R W 2 AE2 1 0 R W 1 AE1 0 R W Bit Initial value R W PFCR is an 8 bit readable writeable register that performs address output control in extension modes involving ROM PFCR is initialized to H 0D H 00 by a reset and in the hardware standby mode Bits 7 to...

Page 115: ...t disabled 1 0 0 0 A8 A15 address output enabled A16 A23 address output disabled 1 A8 A16 address output enabled A17 A23 address output disabled 1 0 A8 A17 address output enabled A18 A23 address output disabled 1 A8 A18 address output enabled A19 A23 address output disabled 1 0 0 A8 A19 address output enabled A20 A23 address output disabled 1 A8 A20 address output enabled A21 A23 address output di...

Page 116: ...it access to all areas However note that if 16 bit access is designated by the bus controller for any area the bus mode switches to 16 bits and port E becomes a data bus 3 3 3 Mode 6 The CPU can access a 16 Mbyte address space in advanced mode The on chip ROM is enabled Ports A B and C function as input port pins immediately after a reset Address output can be performed by setting the correspondin...

Page 117: ... P Port D D D D P Port E P D P D P D P Port F PF7 P C P C P C P C PF6 to PF4 C C C P PF3 P C P C P C PF2 P C P C P C Legend P I O port A Address bus output D Data bus I O C Control signals clock I O After reset 3 5 Address Map in Each Operating Mode A address maps of the H8S 2646 Series are shown in figures 3 1 1 and 3 1 2 The address space is 16 Mbytes in modes 4 to 7 advanced modes The address s...

Page 118: ... H FFE000 H FFDFFF H FFE000 H FFDFFF H FFB000 H FFAFFF H FFE000 H FFEFC0 H FFF800 H FFFF40 H FFFF60 H FFFFC0 H FFFF60 H FFFFC0 On chip RAM Reserved area On chip RAM External address space External address space External address space Internal I O registers H FFFFFF H FFFFFF H FFF800 H FFFF3F External addresses can be accessed by clearing th RAME bit in SYSCR to 0 Modes 4 and 5 advanced expanded mo...

Page 119: ...FFFF40 H FFFF60 H FFFFC0 H FFE800 H FFE7FF H 00FFFF H 010000 H FFE800 H FFE7FF H FFB000 H FFAFFF H FFE000 H FFEFC0 H FFF800 H FFFF40 H FFFF60 H FFFFC0 H FFFF60 H FFFFC0 On chip RAM Reserved area On chip RAM External address space External address space External address space Internal I O registers H FFFFFF H FFFFFF H FFF800 H FFFF3F External addresses can be accessed by clearing th RAME bit in SYS...

Page 120: ...88 ...

Page 121: ...fter a low to high transition at the RES pin or when the watchdog overflows The CPU enters the reset state when the RES pin is low Trace 1 Starts when execution of the current instruction or exception handling ends if the trace T bit is set to 1 Direct transition Starts when a direct transition occurs due to execution of a SLEEP instruction Interrupt Starts when execution of the current instructio...

Page 122: ...n starts from that address For a reset exception steps 2 and 3 above are carried out 4 1 3 Exception Vector Table The exception sources are classified as shown in figure 4 1 Different vector addresses are assigned to different exception sources Table 4 2 lists the exception sources and their vector addresses Exception sources Reset Trace Interrupts Trap instruction External interrupts NMI IRQ5 to ...

Page 123: ...C to H 002F Reserved for system use 12 H 0030 to H 0033 13 H 0034 to H 0037 14 H 0038 to H 003B 15 H 003C to H 003F External interrupt IRQ0 16 H 0040 to H 0043 IRQ1 17 H 0044 to H 0047 IRQ2 18 H 0048 to H 004B IRQ3 19 H 004C to H 004F IRQ4 20 H 0050 to H 0053 IRQ5 21 H 0054 to H 0057 Reserved for system use 22 H 0058 to H 005B 23 H 005C to H 005F Internal interrupt 2 24 127 H 0060 to H 0063 H 01FC...

Page 124: ... Sequence This LSI enters reset state when the RES pin goes low To ensure that this LSI is reset hold the RES pin low for at least 20 ms at power up To reset during operation hold the RES pin low for at least 20 states When the RES pin goes high after being held low for the necessary time this LSI starts reset exception handling as follows 1 The internal state of the CPU and the registers of the o...

Page 125: ... 5 High Internal processing Prefetch of first program instruction 2 4 1 3 Reset exception handling vector address when reset 1 H 000000 3 H 000002 2 4 Start address contents of reset exception handling vector address 5 Start address 5 2 4 6 First program instruction 6 Figure 4 2 Reset Sequence Modes 6 and 7 ...

Page 126: ... 3 program wait states are inserted Figure 4 3 Reset Sequence Mode 4 4 2 3 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer SP is initialized the PC and CCR will not be saved correctly leading to a program crash To prevent this all interrupt requests including NMI are disabled immediately after a reset Since the first instruction of a program is always ...

Page 127: ... bit in EXR is set to 1 trace mode is activated In trace mode a trace exception occurs on completion of each instruction Trace mode is canceled by clearing the T bit in EXR to 0 It is not affected by interrupt masking Table 4 3 shows the state of CCR and EXR after execution of trace exception handling Interrupts are accepted even within the trace exception handling routine The T bit saved on the s...

Page 128: ...r control PWM timer Each interrupt source has a separate vector address NMI is the highest priority interrupt Interrupts are controlled by the interrupt controller The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority mask levels to enable multiplexed interrupt control For details of interrupts see section 5 Interrupt Controller Interru...

Page 129: ...etches a start address from a vector table entry corresponding to a vector number from 0 to 3 as specified in the instruction code Table 4 4 shows the status of CCR and EXR after execution of trap instruction exception handling Table 4 4 Status of CCR and EXR after Trap Instruction Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T 0 1 2 1 0 Legend 1 Set to 1 0 Cleared to 0 Retains ...

Page 130: ... PC 16 bits Reserved EXR a Interrupt control mode 0 b Interrupt control mode 2 Note Ignored on return Figure 4 5 1 Stack Status after Exception Handling Normal Modes Not Available in the H8S 2646 Series SP SP CCR PC 24 bits CCR PC 24 bits Reserved EXR a Interrupt control mode 0 b Interrupt control mode 2 Note Ignored on return Figure 4 5 2 Stack Status after Exception Handling Advanced Modes ...

Page 131: ...owing instructions to restore registers POP W Rn or MOV W SP Rn POP L ERn or MOV L SP ERn Setting SP to an odd value may lead to a malfunction Figure 4 6 shows an example of what happens when the SP value is odd SP Legend Note This diagram illustrates an example in which the interrupt control mode is 0 in advanced mode SP SP CCR PC R1L PC H FFFEFA H FFFEFB H FFFEFC H FFFEFD H FFFEFF MOV B R1L ER7 ...

Page 132: ...100 ...

Page 133: ...s Eight priority levels can be set for each module for all interrupts except NMI NMI is assigned the highest priority level of 8 and can be accepted at all times Independent vector addresses All interrupt sources are assigned independent vector addresses making it unnecessary for the source to be identified in the interrupt handling routine Seven external interrupts NMI is the highest priority int...

Page 134: ...INTM1 INTM0 NMIEG NMI input unit IRQ input unit ISR ISCR IER IPR Interrupt controller Priority determination Interrupt request Vector number I I2 to I0 CCR EXR CPU ISCR IER ISR IPR SYSCR IRQ sense control register IRQ enable register IRQ status register Interrupt priority register System control register Legend Figure 5 1 Block Diagram of Interrupt Controller ...

Page 135: ...sense control register H ISCRH R W H 00 H FE12 IRQ sense control register L ISCRL R W H 00 H FE13 IRQ enable register IER R W H 00 H FE14 IRQ status register ISR R W 2 H 00 H FE15 Interrupt priority register A IPRA R W H 77 H FEC0 Interrupt priority register B IPRB R W H 77 H FEC1 Interrupt priority register C IPRC R W H 77 H FEC2 Interrupt priority register D IPRD R W H 77 H FEC3 Interrupt priori...

Page 136: ...in hardware standby mode SYSCR is not initialized in software standby mode Bits 5 and 4 Interrupt Control Mode 1 and 0 INTM1 INTM0 These bits select one of two interrupt control modes for the interrupt controller Bit 5 Bit 4 Interrupt INTM1 INTM0 Control Mode Description 0 0 0 Interrupts are controlled by I bit Initial value 1 Setting prohibited 1 0 2 Interrupts are controlled by bits I2 to I0 and...

Page 137: ...ode Bits 7 and 3 Reserved These bits are always read as 0 and cannot be modified Table 5 3 Correspondence between Interrupt Sources and IPR Settings Bits Register 6 to 4 2 to 0 IPRA IRQ0 IRQ1 IPRB IRQ2 IRQ4 IRQ3 IRQ5 IPRC 1 DTC IPRD Watchdog timer 0 1 IPRE PC break A D converter Watchdog timer 1 IPRF TPU channel 0 TPU channel 1 IPRG TPU channel 2 TPU channel 3 IPRH TPU channel 4 TPU channel 5 IPRJ...

Page 138: ...extend register EXR in the CPU and if the priority level of the interrupt is higher than the set mask level an interrupt request is issued to the CPU 5 2 3 IRQ Enable Register IER 7 0 R W 6 0 R W 5 IRQ5E 0 R W 4 IRQ4E 0 R W 3 IRQ3E 0 R W 0 IRQ0E 0 R W 2 IRQ2E 0 R W 1 IRQ1E 0 R W Bit Initial value R W IER is an 8 bit readable writable register that controls enabling and disabling of interrupt reque...

Page 139: ...ing for the input at pins IRQ5 to IRQ0 The ISCR registers are initialized to H 0000 by a reset and in hardware standby mode Bits 15 to 12 Reserved These bits are always read as 0 and should only be written with 0 Bits 11 to 0 IRQ5 Sense Control A and B IRQ5SCA IRQ5SCB to IRQ0 Sense Control A and B IRQ0SCA IRQ0SCB Bits 11 to 0 IRQ5SCB to IRQ0SCB IRQ5SCA to IRQ0SCA Description 0 0 Interrupt request ...

Page 140: ...tions Initial value Cleared by reading IRQnF flag when IRQnF 1 then writing 0 to IRQnF flag When interrupt exception handling is executed when low level detection is set IRQnSCB IRQnSCA 0 and IRQn input is high When IRQn interrupt exception handling is executed when falling rising or both edge detection is set IRQnSCB 1 or IRQnSCA 1 When the DTC is activated by an IRQn interrupt and the DISEL bit ...

Page 141: ...e or a falling edge on the NMI pin The vector number for NMI interrupt exception handling is 7 IRQ5 to IRQ0 Interrupts Interrupts IRQ5 to IRQ0 are requested by an input signal at pins IRQ5 to IRQ0 Interrupts IRQ5 to IRQ0 have the following features Using ISCR it is possible to select whether an interrupt is generated by a low level falling edge rising edge or both edges at pins IRQ5 to IRQ0 Enabli...

Page 142: ...here are flags that indicate the interrupt request status and enable bits that select enabling or disabling of these interrupts If both of these are set to 1 for a particular interrupt source an interrupt request is issued to the interrupt controller The interrupt priority level can be set by means of IPR The DTC can be activated by a TPU SCI or other interrupt request When the DTC is activated by...

Page 143: ...upt end DTC 24 H 0060 IPRC2 to 0 WOVI0 interval timer Watchdog timer 0 25 H 0064 IPRD6 to 4 Reserved for system use 26 H 0068 PC break PC break controller 27 H 006C IPRE6 to 4 ADI A D conversion end A D 28 H 0070 IPRE2 to 0 WOVI1 interval timer Watchdog timer 1 29 H 0074 Reserved for system use 30 31 H 0078 H 007C TGI0A TGR0A input capture compare match TGI0B TGR0B input capture compare match TGI0...

Page 144: ...ture compare match TGI3B TGR3B input capture compare match TGI3C TGR3C input capture compare match TGI3D TGR3D input capture compare match TCI3V overflow 3 TPU channel 3 48 49 50 51 52 H 00C0 H 00C4 H 00C8 H 00CC H 00D0 IPRG2 to 0 Reserved for system use 53 to 55 H 00D4 to H 00DC TGI4A TGR4A input capture compare match TGI4B TGR4B input capture compare match TCI4V overflow 4 TCI4U underflow 4 TPU ...

Page 145: ...eption completed 2 TXI2 transmit data empty 2 TEI2 transmission end 2 SCI channel 2 2 88 89 90 91 H 0160 H 0164 H 0168 H 016C IPRK2 to 0 Reserved for system use 92 to 103 H 0170 to H 019C CMI1 PWCYR1 compare match CMI2 PWCYR2 compare match PWM 104 105 H 01A0 H 01A4 IPRM6 to 4 Reserved for system use 106 107 H 01A8 H 01AC ERS0 OVR0 RM1 SLE0 RM0 mailbox 0 reception HCAN 108 109 H 01B0 H 01B4 IPRM2 t...

Page 146: ...bits are set to 1 are controlled by the interrupt controller Table 5 5 shows the interrupt control modes The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR the priorities set in IPR and the masking state indicated by the I bit in the CPU s CCR and bits I2 to I0 in EXR Table 5 5 Interrupt Control Modes Interrupt SYSCR...

Page 147: ...e 0 I Figure 5 4 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control In interrupt control mode 0 interrupt acceptance is controlled by the I bit in CCR Table 5 6 shows the interrupts selected in each interrupt control mode Table 5 6 Interrupts Selected in Each Interrupt Control Mode 1 Interrupt Mask Bits Interrupt Control Mode I Selected Interrupts 0 0 All interrupts 1 NMI in...

Page 148: ...or number is generated If the same value is set for IPR acceptance of multiple interrupts is enabled and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated Interrupt sources with a lower priority than the accepted interrupt source are held pending Table 5 8 shows operations and control signal functions in ...

Page 149: ... and other interrupt requests are held pending 3 Interrupt requests are sent to the interrupt controller the highest ranked interrupt according to the priority system is accepted and other interrupt requests are held pending 4 When an interrupt request is accepted interrupt exception handling starts after execution of the current instruction has been completed 5 The PC and CCR are saved to the sta...

Page 150: ...ated NMI IRQ0 IRQ1 HCAN I 0 Save PC and CCR I 1 Read vector address Branch to interrupt handling routine Yes No Yes Yes Yes No No No Yes Yes No Hold pending Figure 5 5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 ...

Page 151: ...le 5 4 is selected 3 Next the priority of the selected interrupt request is compared with the interrupt mask level set in EXR An interrupt request with a priority no higher than the mask level set at that time is held pending and only an interrupt request with a priority higher than the interrupt mask level is accepted 4 When an interrupt request is accepted interrupt exception handling starts aft...

Page 152: ...ask level 6 or below Save PC CCR and EXR Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Hold pending Level 1 interrupt Mask level 0 Yes Yes No Yes Yes Yes No Yes Yes No No No No No No Figure 5 6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 ...

Page 153: ...tance Interrupt level determination Wait for end of instruction Interrupt request signal Internal address bus Internal read signal Internal write signal Internal data us ø 3 1 2 4 3 5 7 Instruction prefetch address Not executed This is the contents of the saved PC the return address Instruction code Not executed Instruction prefetch address Not executed SP 2 SP 4 Saved PC and saved CCR Vector addr...

Page 154: ...anced Mode No Execution Status INTM1 0 INTM1 1 INTM1 0 INTM1 1 1 Interrupt priority determination 1 3 3 3 3 2 Number of wait states until executing instruction ends 2 1 to 19 2 SI 1 to 19 2 SI 1 to 19 2 SI 1 to 19 2 SI 3 PC CCR EXR stack save 2 SK 3 SK 2 SK 3 SK 4 Vector fetch SI SI 2 SI 2 SI 5 Instruction fetch 3 2 SI 2 SI 2 SI 2 SI 6 Internal processing 4 2 2 2 2 Total using on chip memory 11 to...

Page 155: ...cution of the instruction In other words when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV if an interrupt is generated during execution of the instruction the interrupt concerned will still be enabled on completion of the instruction and so interrupt exception handling for that interrupt will be executed on completion of the instruction However if there is an inte...

Page 156: ... that disable interrupts are LDC ANDC ORC and XORC After any of these instructions is executed all interrupts including NMI are disabled and the next instruction is always executed When the I bit is set by one of these instructions the new value becomes valid two states after execution of the instruction ends 5 5 3 Times when Interrupts are Disabled There are times when interrupt acceptance is dis...

Page 157: ...on of an EEPMOV W instruction the following coding should be used L1 EEPMOV W MOV W R4 R4 BNE L1 5 5 5 IRQ Interrupts When operating by clock input acceptance of input to an IRQ pin is synchronized with the clock In software standby mode the input is accepted asynchronously For details on the input conditions see section 23 4 2 Control Signal Timing 5 6 DTC Activation by Interrupt 5 6 1 Overview T...

Page 158: ...t is possible to clear the DTCE bit to 0 after DTC data transfer and request a CPU interrupt If DTC carries out the designate number of data transfers and the transfer counter reads 0 after DTC data transfer the DTCE bit is also cleared to 0 and a CPU interrupt requested Determination of Priority The DTC activation source is selected in accordance with the default priority order and is not affecte...

Page 159: ...evant interrupt is used Interrupt source clearing is performed The CPU should clear the source flag in the interrupt handling routine The relevant interrupt is used The interrupt source is not cleared X The relevant bit cannot be used Don t care Notes on Use SCI and A D converter interrupt sources are cleared when the DTC reads or writes to the prescribed register ...

Page 160: ...128 ...

Page 161: ...break channels A and B The following can be set as break compare conditions 24 address bits Bit masking possible Bus cycle Instruction fetch Data access data read data write data read write Bus master Either CPU or CPU DTC can be selected The timing of PC break exception handling after the occurrence of a break condition is as follows Immediately before execution of the instruction fetched at the ...

Page 162: ... break controller Output control Mask control Output control Match signal PC break interrupt Match signal Mask control BARA BCRA BARB BCRB Comparator Control logic Comparator Control logic Internal address Access status Figure 6 1 Block Diagram of PC Break Controller ...

Page 163: ... flag 6 2 Register Descriptions 6 2 1 Break Address Register A BARA Bit Initial value Read Write 31 Unde fined 24 Unde fined R W BAA 23 23 0 R W BAA 22 22 0 R W BAA 21 21 0 R W BAA 20 20 0 R W BAA 19 19 0 R W BAA 18 18 0 R W BAA 17 17 0 R W BAA 16 16 0 R W 0 BAA 7 7 R W 0 BAA 6 6 R W 0 BAA 5 5 R W 0 BAA 4 4 R W 0 BAA 3 3 R W 0 BAA 2 2 R W 0 BAA 1 1 R W 0 BAA 0 0 BARA is a 32 bit readable writable ...

Page 164: ...n masking and 3 specifies whether the break condition is applied to an instruction fetch or a data access It also contains a condition match flag BCRA is initialized to H 00 by a reset and in hardware standby mode Bit 7 Condition Match Flag A CMFA Set to 1 when a break condition set for channel A is satisfied This flag is not cleared to 0 Bit 7 CMFA Description 0 Clearing condition When 0 is writt...

Page 165: ...asked and not included in break conditions 1 0 BAA11 0 lower 12 bits are masked and not included in break conditions 1 BAA15 0 lower 16 bits are masked and not included in break conditions Bits 2 and 1 Break Condition Select A CSELA1 CSELA0 These bits selection an instruction fetch data read data write or data read write cycle as the channel A break condition Bit 2 Bit 1 CSELA1 CSELA0 Description ...

Page 166: ...e stop mode control When the MSTPC4 bit is set to 1 PC break controller operation is stopped at the end of the bus cycle and module stop mode is entered Register read write accesses are not possible in module stop mode For details see section 22 5 Module Stop Mode MSTPCRC is initialized to H FF by a reset and in hardware standby mode It is not initialized in software standby mode Bit 4 Module Stop...

Page 167: ... condition BCRA bit 0 BIEA Set to 1 to enable break interrupts 2 Satisfaction of break condition When the instruction at the set address is fetched a PC break request is generated immediately before execution of the fetched instruction and the condition match flag CMFA is set 3 Interrupt handling After priority determination by the interrupt controller PC break interrupt exception handling is star...

Page 168: ...controller 6 3 4 Operation in Transitions to Power Down Modes The operation when a PC break interrupt is set for an instruction fetch at the address after a SLEEP instruction is shown below 1 When the SLEEP instruction causes a transition from high speed medium speed mode to sleep mode or from subactive mode to subsleep mode After execution of the SLEEP instruction a transition is not made to slee...

Page 169: ...lock system clock oscillation settling time SLEEP instruction execution Transition to respective mode Direct transition exception handling PC break exception handling Execution of instruction after sleep instruction PC break exception handling Execution of instruction after sleep instruction A B C D SLEEP instruction execution Figure 6 2 Operation in Power Down Mode Transitions 6 3 5 PC Break Oper...

Page 170: ...later than in normal operation 3 When break interruption by instruction fetch is set and a break interrupt is generated if the executing instruction immediately preceding the set instruction has one of the addressing modes shown below and that address indicates on chip ROM or RAM and that address is used for data access the instruction will be one state later than in normal operation ERn d 16 ERn ...

Page 171: ...ince interrupts including NMI are disabled for a 3 state period in the case of LDC ANDC ORC and XORC the next instruction is always executed For details see section 5 Interrupt Controller 3 When a PC break is set for an instruction fetch at the address following a Bcc instruction A PC break interrupt is generated if the instruction at the next address is executed in accordance with the branch cond...

Page 172: ...140 ...

Page 173: ...ytes Bus specifications can be set independently for each area Burst ROM interface can be set Basic bus interface 8 bit access or 16 bit access can be selected for each area 2 state access or 3 state access can be selected for each area Program wait states can be inserted for each area Burst ROM interface Burst ROM interface can be set for area 0 Choice of 1 or 2 state burst access Idle cycle inse...

Page 174: ... control register ASTCR Access state control register BCRH Bus control register H BCRL Bus control register L WCRH Wait control register H WCRL Wait control register L Internal control signals Wait controller WCRH WCRL Bus mode signal Bus arbiter CPU bus request signal DTC bus request signal CPU bus acknowledge signal DTC bus acknowledge signal Internal data bus Figure 7 1 Block Diagram of Bus Con...

Page 175: ...n and lower half D7 to D0 of data bus is enabled Wait WAIT Input Wait request signal used when accessing external 3 state access space 7 1 4 Register Configuration Table 7 2 summarizes the registers of the bus controller Table 7 2 Bus Controller Registers Name Abbreviation R W Initial Value Address 1 Bus width control register ABWCR R W H FF H 00 2 H FED0 Access state control register ASTCR R W H ...

Page 176: ...ettings in ABWCR After a reset and in hardware standby mode ABWCR is initialized to H FF in modes 5 6 7 and to H 00 in mode 4 It is not initialized in software standby mode Bits 7 to 0 Area 7 to 0 Bus Width Control ABW7 to ABW0 These bits select whether the corresponding area is to be designated for 8 bit access or 16 bit access Bit n ABWn Description 0 Area n is designated for 16 bit access 1 Are...

Page 177: ...standby mode Bits 7 to 0 Area 7 to 0 Access State Control AST7 to AST0 These bits select whether the corresponding area is to be designated as a 2 state access space or a 3 state access space Wait state insertion is enabled or disabled at the same time Bit n ASTn Description 0 Area n is designated for 2 state access Wait state insertion in area n external space is disabled 1 Area n is designated f...

Page 178: ...n ASTCR is set to 1 Bit 7 Bit 6 W71 W70 Description 0 0 Program wait not inserted when external space area 7 is accessed 1 1 program wait state inserted when external space area 7 is accessed 1 0 2 program wait states inserted when external space area 7 is accessed 1 3 program wait states inserted when external space area 7 is accessed Initial value Bits 5 and 4 Area 6 Wait Control 1 and 0 W61 W60...

Page 179: ...ea 5 is accessed 1 3 program wait states inserted when external space area 5 is accessed Initial value Bits 1 and 0 Area 4 Wait Control 1 and 0 W41 W40 These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1 Bit 1 Bit 0 W41 W40 Description 0 0 Program wait not inserted when external space area 4 is accessed 1 1 program w...

Page 180: ...ssed 1 0 2 program wait states inserted when external space area 3 is accessed 1 3 program wait states inserted when external space area 3 is accessed Initial value Bits 5 and 4 Area 2 Wait Control 1 and 0 W21 W20 These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1 Bit 5 Bit 4 W21 W20 Description 0 0 Program wait not...

Page 181: ...ea 1 is accessed 1 3 program wait states inserted when external space area 1 is accessed Initial value Bits 1 and 0 Area 0 Wait Control 1 and 0 W01 W00 These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1 Bit 1 Bit 0 W01 W00 Description 0 0 Program wait not inserted when external space area 0 is accessed 1 1 program w...

Page 182: ...s Bit 7 ICIS1 Description 0 Idle cycle not inserted in case of successive external read cycles in different areas 1 Idle cycle inserted in case of successive external read cycles in different areas Initial value Bit 6 Idle Cycle Insert 0 ICIS0 Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed Bit 6...

Page 183: ... 7 2 5 Bus Control Register L BCRL 7 0 R W 6 0 R W 5 0 4 0 R W 3 1 R W 0 WAITE 0 R W 2 0 R W 1 WDBE 0 R W Bit Initial value R W BCRL is an 8 bit readable writable register that performs selection of the external bus released state protocol enabling or disabling of the write data buffer function BCRL is initialized to H 08 by a reset and in hardware standby mode It is not initialized in software st...

Page 184: ...cription 0 Wait input by WAIT pin disabled WAIT pin can be used as I O port Initial value 1 Wait input by WAIT pin enabled 7 2 6 Pin Function Control Register PFCR 7 0 R W 6 0 R W 5 0 R W 4 0 R W 3 AE3 1 0 R W 0 AE0 1 0 R W 2 AE2 1 0 R W 1 AE1 0 R W Bit Initial value R W PFCR is an 8 bit read write register that controls the address output in expanded mode with ROM PFCR is initialized to H 0D H 00...

Page 185: ...isabled 1 A8 A12 address output enabled A13 A23 address output disabled 1 0 A8 A13 address output enabled A14 A23 address output disabled 1 A8 A14 address output enabled A15 A23 address output disabled 1 0 0 0 A8 A15 address output enabled A16 A23 address output disabled 1 A8 A16 address output enabled A17 A23 address output disabled 1 0 A8 A17 address output enabled A18 A23 address output disable...

Page 186: ...ing part of area 0 Figure 7 2 shows an outline of the memory map Note Not available in the H8S 2646 Series Area 0 2Mbytes H 000000 H FFFFFF 1 2 H 0000 H 1FFFFF H 200000 Area 1 2Mbytes H 3FFFFF H 400000 Area 2 2Mbytes H 5FFFFF H 600000 Area 3 2Mbytes H 7FFFFF H 800000 Area 4 2Mbytes H 9FFFFF H A00000 Area 5 2Mbytes H BFFFFF H C00000 Area 6 2Mbytes H DFFFFF H E00000 Area 7 2Mbytes H FFFF Advanced mo...

Page 187: ...d for 16 bit access 16 bit bus mode is set When the burst ROM interface is designated 16 bit bus mode is always set Number of Access States Two or three access states can be selected with ASTCR An area for which 2 state access is selected functions as a 2 state access space and an area for which 3 state access is selected functions as a 3 state access space With the burst ROM interface the number ...

Page 188: ...2 1 3 7 3 3 Memory Interfaces The H8S 2646 Series memory interfaces comprise a basic bus interface that allows direct connection or ROM SRAM and so on and a burst ROM interface that allows direct connection of burst ROM The memory interface can be selected independently for each area An area for which the basic bus interface is designated functions as normal space and an area for which the burst R...

Page 189: ...expansion mode the space excluding on chip ROM is external space Either basic bus interface or burst ROM interface can be selected for area 0 Areas 1 to 6 In external expansion mode all of areas 1 to 6 is external space Only the basic bus interface can be used for areas 1 to 6 Area 7 Area 7 includes the on chip RAM and internal I O registers In external expansion mode the space excluding the on ch...

Page 190: ...bus specifications for the area being accessed 8 bit access space or 16 bit access space and the data size 8 Bit Access Space Figure 7 3 illustrates data alignment control for the 8 bit access space With the 8 bit access space the upper data bus D15 to D8 is always used for accesses The amount of data that can be accessed at one time is one byte a word transfer instruction is performed as two byte...

Page 191: ...a longword transfer instruction is executed as two word transfer instructions In byte access whether the upper or lower data bus is used is determined by whether the address is even or odd The upper data bus is used for an even address and the lower data bus for an odd address D15 D8 D7 D0 Upper data bus Byte size Word size 1st bus cycle 2nd bus cycle Longword size Even address Byte size Odd addre...

Page 192: ...s and the LWR signal for the lower half Table 7 4 Data Buses Used and Valid Strobes Area Access Size Read Write Address Valid Strobe Upper Data Bus D15 to D8 Lower data bus D7 to D0 8 bit access Byte Read RD Valid Invalid space Write HWR Hi Z 16 bit access Byte Read Even RD Valid Invalid space Odd Invalid Valid Write Even HWR Valid Hi Z Odd LWR Hi Z Valid Word Read RD Valid Valid Write HWR LWR Val...

Page 193: ...n 8 bit access space is accessed the upper half D15 to D8 of the data bus is used The LWR pin is fixed high Wait states cannot be inserted Bus cycle T1 T2 Address bus ø AS RD D15 to D8 Valid D7 to D0 Invalid Read HWR LWR D15 to D8 Valid D7 to D0 High impedance Write High Figure 7 5 Bus Timing for 8 Bit 2 State Access Space ...

Page 194: ...cess space is accessed the upper half D15 to D8 of the data bus is used The LWR pin is fixed high Wait states can be inserted Bus cycle T1 T2 Address bus ø AS RD D15 to D8 Valid D7 to D0 Invalid Read HWR LWR D15 to D8 Valid D7 to D0 High impedance Write High T3 Figure 7 6 Bus Timing for 8 Bit 3 State Access Space ...

Page 195: ...half D15 to D8 of the data bus is used for the even address and the lower half D7 to D0 for the odd address Wait states cannot be inserted Bus cycle T1 T2 Address bus ø AS RD D15 to D8 Valid D7 to D0 Invalid Read HWR D15 to D8 Valid D7 to D0 High impedance Write LWR High Figure 7 7 Bus Timing for 16 Bit 2 State Access Space 1 Even Address Byte Access ...

Page 196: ... cycle T1 T2 Address bus ø AS RD D15 to D8 Invalid D7 to D0 Valid Read HWR LWR D15 to D8 High impedance D7 to D0 Valid Write High Figure 7 8 Bus Timing for 16 Bit 2 State Access Space 2 Odd Address Byte Access ...

Page 197: ...165 Bus cycle T1 T2 Address bus ø AS RD D15 to D8 Valid D7 to D0 Valid Read HWR LWR D15 to D8 Valid D7 to D0 Valid Write Figure 7 9 Bus Timing for 16 Bit 2 State Access Space 3 Word Access ...

Page 198: ... half D15 to D8 of the data bus is used for the even address and the lower half D7 to D0 for the odd address Wait states can be inserted Bus cycle T1 T2 Address bus ø AS RD D15 to D8 Valid D7 to D0 Invalid Read HWR LWR D15 to D8 Valid D7 to D0 High impedance Write High T3 Figure 7 10 Bus Timing for 16 Bit 3 State Access Space 1 Even Address Byte Access ...

Page 199: ...ycle T1 T2 Address bus ø AS RD D15 to D8 Invalid D7 to D0 Valid Read HWR LWR D15 to D8 High impedance D7 to D0 Valid Write High T3 Figure 7 11 Bus Timing for 16 Bit 3 State Access Space 2 Odd Address Byte Access ...

Page 200: ...168 Bus cycle T1 T2 Address bus ø AS RD D15 to D8 Valid D7 to D0 Valid Read HWR LWR D15 to D8 Valid D7 to D0 Valid Write T3 Figure 7 12 Bus Timing for 16 Bit 3 State Access Space 3 Word Access ...

Page 201: ...tings of WCRH and WCRL Pin Wait Insertion Setting the WAITE bit in BCRH to 1 enables wait input by means of the WAIT pin When external space is accessed in this state a program wait is first inserted in accordance with the settings in WCRH and WCRL If the WAIT pin is low at the falling edge of ø in the last T2 or Tw state another Tw state is inserted If the WAIT pin is held low Tw states are inser...

Page 202: ...pin T1 Address bus WAIT ø AS RD Data bus Read data Read HWR LWR Write data Write Note Downward arrows show the timing of WAIT pin sampling Data bus T2 Tw Tw Tw T3 Figure 7 13 Example of Wait State Insertion Timing The settings after a reset are 3 state access 3 program wait state insertion ...

Page 203: ...f access states in the initial cycle full access of the burst ROM interface Wait states can be inserted when the AST0 bit is set to 1 The burst cycle can be set for 1 state or 2 sttes by setting the BRSTS1 bit of BCRH Wait states cannot be inserted When area 0 is set as burst ROM space area 0 is a 16 bit access space regardless of the ABW0 bit of ABWCR When the BRSTS0 bit of BCRH is cleared to 0 4...

Page 204: ...ress only changes Read data Read data Read data Figure 7 14 a Example Burst ROM Access Timing AST0 BRSTS1 1 T1 Address bus ø AS Data bus T2 T1 T1 Full access RD Burst access Low address only changes Read data Read data Read data Figure 7 14 b Example Burst ROM Access Timing AST0 BRSTS1 0 ...

Page 205: ...basic bus interface either program wait insertion or pin wait insertion using the WAIT pin can be used in the burst ROM interface initial cycle full access See section 7 4 5 Wait Control Wait states cannot be inserted in the burst cycle ...

Page 206: ...the second read cycle Figure 7 15 shows an example of the operation in this case In this example bus cycle A is a read cycle from ROM with a long output floating time and bus cycle B is a read cycle from SRAM each being located in a different area In a an idle cycle is not inserted and a collision occurs in cycle B between the read data from ROM and that from SRAM In b an idle cycle is inserted an...

Page 207: ... is not inserted and a collision occurs in cycle B between the read data from ROM and the CPU write data In b an idle cycle is inserted and a data collision is prevented T1 Address bus Note The CS signal is generated externally rather than inside the LSI device ø RD Bus cycle A T2 T3 T1 T2 Bus cycle B Possibility of overlap between CS area B and RD T1 Address bus ø Bus cycle A T2 T3 TI T1 Bus cycl...

Page 208: ... between the RD and CS signals In the initial state after reset release idle cycle insertion b is set Note The CS signal is generated externally rather than inside the LSI device T1 Address bus ø RD Bus cycle A Data bus T2 T3 T1 T2 Bus cycle B Long output floating time Data collision T1 Address bus ø RD Bus cycle A Data bus T2 T3 TI T1 Bus cycle B T2 HWR HWR CS area A CS area B CS area A CS area B...

Page 209: ...e 7 5 shows the pin states during idle cycles Table 7 5 Pin States During Idle Cycles Pins Pin State A23 to A0 Content identical to immediately following bus cycle D15 to D0 High impedance AS High level RD High level HWR High level LWR High level ...

Page 210: ...l write continues for 2 states or longer and there is an internal access next only an external write is executed in the first state but from the next state onward an internal access on chip memory or internal I O register read write is executed in parallel with the external write rather than waiting until it ends T1 Internal address bus A23 to A0 External write cycle HWR LWR T2 TW TW T3 On chip me...

Page 211: ...ession of the bus until that signal is canceled The order of priority of the bus masters is as follows High DTC CPU Low 7 8 3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating the bus is not necessarily transferred immediately There are specific times at which each bus mast...

Page 212: ...rmation write 3 states It does not release the bus during a register information read 3 states a single data transfer or a register information write 3 states 7 9 Resets and the Bus Controller In a reset the H8S 2646 Series including the bus controller enters the reset state at that point and an executing bus cycle is discontinued ...

Page 213: ...rementing and fixing of source and destination addresses can be selected Direct specification of 16 Mbyte address space possible 24 bit transfer source and destination addresses can be specified Transfer can be set in byte or word units A CPU interrupt can be requested for the interrupt that activated the DTC An interrupt request can be issued to the CPU after one data transfer ends An interrupt r...

Page 214: ...R must be set to 1 Interrupt request Interrupt controller DTC Internal address bus DTC service request Control logic Register information MRA MRB CRA CRB DAR SAR CPU interrupt request On chip RAM Internal data bus Legend MRA MRB CRA CRB SAR DAR DTCERA to DTCERG I DTVECR DTCERA to DTCERG DTCERI DTVECR DTC mode registers A and B DTC transfer count registers A and B DTC source address register DTC de...

Page 215: ...nsfer count register A CRA 2 Undefined 3 DTC transfer count register B CRB 2 Undefined 3 DTC enable registers DTCER R W H 00 H FE16 to H FE1E DTC vector register DTVECR R W H 00 H FE1F Module stop control register A MSTPCRA R W H 3F H FDE8 Notes 1 Lower 16 bits of the address 2 Registers within the DTC cannot be read or written to directly 3 Register information is located in on chip RAM addresses...

Page 216: ...data transfer Bit 7 Bit 6 SM1 SM0 Description 0 SAR is fixed 1 0 SAR is incremented after a transfer by 1 when Sz 0 by 2 when Sz 1 1 SAR is decremented after a transfer by 1 when Sz 0 by 2 when Sz 1 Bits 5 and 4 Destination Address Mode 1 and 0 DM1 DM0 These bits specify whether DAR is to be incremented decremented or left fixed after a data transfer Bit 5 Bit 4 DM1 DM0 Description 0 DAR is fixed ...

Page 217: ... DTS Specifies whether the source side or the destination side is set to be a repeat area or block area in repeat mode or block transfer mode Bit 1 DTS Description 0 Destination side is repeat area or block area 1 Source side is repeat area or block area Bit 0 DTC Data Transfer Size Sz Specifies the size of data to be transferred Bit 0 Sz Description 0 Byte size transfer 1 Word size transfer ...

Page 218: ...iption 0 End of DTC data transfer activation waiting state is entered 1 DTC chain transfer new register information is read then data is transferred Bit 6 DTC Interrupt Select DISEL Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer Bit 6 DISEL Description 0 After a data transfer ends the CPU interrupt is disabled unless the transfer counter is 0 the DTC ...

Page 219: ...s a 24 bit register that designates the destination address of data to be transferred by the DTC For word size transfer specify an even destination address 8 2 5 DTC Transfer Count Register A CRA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRAH CRAL Bit Initial value R W Undefined CRA is a 16 bit register that designates the number of times data is to be transferred by the DTC In normal mode the entire ...

Page 220: ... transferred by the DTC in block transfer mode It functions as a 16 bit transfer counter 1 to 65536 that is decremented by 1 every time data is transferred and transfer ends when the count reaches H 0000 8 2 7 DTC Enable Registers DTCER 7 DTCE7 0 R W 6 DTCE6 0 R W 5 DTCE5 0 R W 4 DTCE4 0 R W 3 DTCE3 0 R W 0 DTCE0 0 R W 2 DTCE2 0 R W 1 DTCE1 0 R W Bit Initial value R W The DTC enable registers comp...

Page 221: ... each interrupt controller For DTCE bit setting use bit manipulation instructions such as BSET and BCLR for reading and writing If all interrupts are masked multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register 8 2 8 DTC Vector Register DTVECR 7 SWDTE 0 R W 1 6 DTVEC6 0 R W 2 5 DTVEC5 0 R W 2 4 DTVEC4 0 R W 2 3 DTVEC3 0 R W 2 0 DTV...

Page 222: ...ese bits specify a vector number for DTC software activation The vector address is expressed as H 0400 vector number 1 1 indicates a one bit left shift For example when DTVEC6 to DTVEC0 H 10 the vector address is H 0420 8 2 9 Module Stop Control Register A MSTPCRA 7 MSTPA7 0 R W Bit Initial value Read Write 6 MSTPA6 0 R W 5 MSTPA5 1 R W 4 MSTPA4 1 R W 3 MSTPA3 1 R W 2 MSTPA2 1 R W 1 MSTPA1 1 R W 0...

Page 223: ...191 Bit 6 Module Stop MSTPA6 Specifies the DTC module stop mode Bit 6 MSTPA6 Description 0 DTC module stop mode cleared Initial value 1 DTC module stop mode set ...

Page 224: ... in memory makes it possible to transfer data over any required number of channels Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single activation Figure 8 2 shows a flowchart of DTC operation Start Read DTC vector Next transfer Read register information Data transfer Write register information Clear an activation flag CHNE 1 End No No Yes Yes Transfer Counter...

Page 225: ...ansfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 Up to 65 536 transfers possible Repeat mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 After the specified number of transfers 1 to 256 the initial state resumes and operation continues Block transfer mode One transfer request transfers a block o...

Page 226: ... Source When the DISEL Bit Is 0 and the Specified Number of Transfers Have Not Ended When the DISEL Bit Is 1 or when the Specified Number of Transfers Have Ended Software activation The SWDTE bit is cleared to 0 The SWDTE bit remains set to 1 An interrupt is issued to the CPU Interrupt activation The corresponding DTCER bit remains set to 1 The activation source flag is cleared to 0 The correspond...

Page 227: ...VECR is H 10 the vector address is H 0420 The DTC reads the start address of the register information from the vector address set for each activation source and then reads the register information from that start address The register information can be placed at predetermined addresses in the on chip RAM The start address of the register information should be an integral multiple of four The confi...

Page 228: ...DI A D conversion end A D 28 H 0438 DTCEB6 Reserved 29 to 31 H 043A to H 043E TGI0A GR0A compare match input capture TPU channel 0 32 H 0440 DTCEB5 TGI0B GR0B compare match input capture 33 H 0442 DTCEB4 TGI0C GR0C compare match input capture 34 H 0444 DTCEB3 TGI0D GR0D compare match input capture 35 H 0446 DTCEB2 Reserved 36 to 39 H 0448 to H 044E TGI1A GR1A compare match input capture TPU channe...

Page 229: ...4B compare match input capture 57 H 0472 DTCEC0 Reserved 58 59 H 0474 to H 0476 TGI5A GR5A compare match input capture TPU channel 5 60 H 0478 DTCED5 TGI5B GR5B compare match input capture 61 H 047A DTCED4 Reserved 62 to 80 H 047C to H 04A0 RXI0 reception complete 0 SCI 81 H 04A2 DTCEE3 TXI0 transmit data empty 0 channel 0 82 H 04A4 DTCEE2 Reserved 83 84 H 04A6 to H 04A8 RXI1 reception complete 1 ...

Page 230: ...2 compare match 105 H 04D2 DTCEG6 Reserved 106 to 108 H 04D4 H 04D8 RM0 Mail box 0 HCAN0 109 H 04DA DTCEG2 Reserved 110 to 124 H 04DC H 04FC Low Notes 1 DTCE bits with no corresponding interrupt are reserved and should be written with 0 2 These vectors are used in the H8S 2648 H8S 2648R and H8S 2647 They are reserved in the H8S 2646 H8S 2646R and H8S 2645 ...

Page 231: ...ents of the vector address In the case of chain transfer register information should be located in consecutive areas Locate the register information in the on chip RAM addresses H FFEBC0 to H FFEFBF Register information start address Chain transfer Register information for 2nd transfer in chain transfer MRA SAR MRB DAR CRA CRB 4 bytes Lower address CRA CRB Register information MRA 0 1 2 3 SAR MRB ...

Page 232: ...ster information in normal mode and figure 8 6 shows memory mapping in normal mode Table 8 5 Register Information in Normal Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register A CRA Designates transfer count DTC transfer count register B CRB Not used Transfer SAR DA...

Page 233: ...terrupts cannot be requested when DISEL 0 Table 8 6 lists the register information in repeat mode and figure 8 7 shows memory mapping in repeat mode Table 8 6 Register Information in Repeat Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register AH CRAH Holds number of ...

Page 234: ...xed From 1 to 65 536 transfers can be specified Once the specified number of transfers have ended a CPU interrupt is requested Table 8 7 lists the register information in block transfer mode and figure 8 8 shows memory mapping in block transfer mode Table 8 7 Register Information in Block Transfer Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destina...

Page 235: ...203 Transfer SAR or DAR DAR or SAR Block area First block Nth block Figure 8 8 Memory Mapping in Block Transfer Mode ...

Page 236: ...memory map for chain transfer Source Source Destination Destination DTC vector address Register information start address Register information CHNE 1 Register information CHNE 0 Figure 8 9 Chain Transfer Memory Map In the case of transfer with CHNE set to 1 an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1 and the i...

Page 237: ...on read Transfer information write Data transfer Read Write ø Figure 8 10 DTC Operation Timing Example in Normal Mode or Repeat Mode Read Write Read Write Data transfer Transfer information write Transfer information read Vector read ø DTC activation request DTC request Address Figure 8 11 DTC Operation Timing Example of Block Transfer Mode with Block Size of 2 ...

Page 238: ...ing Example of Chain Transfer 8 3 10 Number of DTC Execution States Table 8 8 lists execution statuses for a single DTC data transfer and table 8 9 shows the number of states required for each execution status Table 8 8 DTC Execution Statuses Mode Vector Read I Register Information Read Write J Data Read K Data Write L Internal Operations M Normal 1 6 1 1 3 Repeat 1 6 1 1 3 Block transfer 1 6 N N ...

Page 239: ...Word data write SL 1 1 4 2 4 6 2m 2 3 m Internal operation SM 1 1 1 1 1 1 1 1 The number of execution states is calculated from the formula below Note that Σ means the sum of all transfers activated by one activation event the number in which the CHNE bit is set to 1 plus 1 Number of execution states I SI 1 Σ J SJ K SK L SL M SM For example when the DTC vector address table is located in on chip R...

Page 240: ... to 0 and a CPU interrupt is requested If the DTC is to continue transferring data set the DTCE bit to 1 Activation by Software The procedure for using the DTC with software activation is as follows 1 Set the MRA MRB SAR DAR CRA and CRB register information in the on chip RAM 2 Set the start address of the register information in the DTC vector address 3 Check that the SWDTE bit is 0 4 Write 1 to ...

Page 241: ... DTCER to 1 4 Set the SCI to the appropriate receive mode Set the RIE bit in SCR to 1 to enable the reception complete RXI interrupt Since the generation of a receive error during the SCI reception operation will disable subsequent reception the CPU should be enabled to accept receive error interrupts 5 Each time reception of one byte of data ends on the SCI the RDRF flag in SSR is set to 1 an RXI...

Page 242: ...dress DM1 DM0 0 normal mode MD1 MD0 0 and word size Sz 1 Set the data table start address in SAR the TGRA address in DAR and the data table size in CRA CRB can be set to any value 3 Locate the TPU transfer register information consecutively after the NDR transfer register information 4 Set the start address of the NDR transfer register information to the DTC vector address 5 Set the bit correspond...

Page 243: ... 1 H 0001 in CRB 2 Set the start address of the register information at the DTC vector address H 04C0 3 Check that the SWDTE bit in DTVECR is 0 Check that there is currently no transfer activated by software 4 Write 1 to the SWDTE bit and the vector number H 60 to DTVECR The write data is H E0 5 Read DTVECR again and check that it is set to the vector number H 60 If it is not this indicates that t...

Page 244: ...END interrupt is generated The interrupt handling routine should clear the SWDTE bit to 0 When the DTC is activated by software an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1 8 5 Usage Notes Module Stop When the MSTPA6 bit in MSTPCRA is set to 1 the DTC clock stops and the DTC enters the module stop state However 1 cannot...

Page 245: ...put pull up control register PCR to control the on off state of MOS input pull up Ports 3 and A to F include an open drain control register ODR that controls the on off state of the output buffer PMOS When ports A to F are used as the output pins for expanded bus control signals they can drive one TTL load plus a 50pF capacitance load Ports other than A to F can drive one TTL load and a 30pF capac...

Page 246: ...output pins PO15 to PO8 and interrupt input pins IRQ0 IRQ1 and 8 bit I O port Port 2 8 bit I O port P27 TIOCB5 P26 TIOCA5 P25 TIOCB4 P24 TIOCA4 P23 TIOCD3 P22 TIOCC3 P21 TIOCB3 P20 TIOCA3 TPU I O pins TIOCB5 TIOCA5 TIOCB4 TIOCA4 TIOCD3 TIOCC3 TIOCB3 TIOCA3 and 8 bit I O port Port 3 8 bit I O port P37 P36 P35 SCK1 IRQ5 P34 RxD1 P33 TxD1 P32 SCK0 IRQ4 P31 RxD0 P30 TxD0 SCI channels 0 1 I O pins TxD0...

Page 247: ... port LCD segment and common output SEG21 to SEG24 COM1 to COM4 and 8 bit I O port Port B 8 bit I O port Built in MOS input pull up Open drain output capability PB7 A15 SEG16 PB6 A14 SEG15 PB5 A13 SEG14 PB4 A12 SEG13 PB3 A11 SEG12 PB2 A10 SEG11 PB1 A9 SEG10 PB0 A8 SEG9 LCD segment output SEG9 to SEG16 address output A15 to A8 and 8 bit I O port LCD segment output SEG9 to SEG16 and 8 bit I O port P...

Page 248: ...DDR 1 φ output PF6 AS SEG20 PF5 RD SEG19 PF4 HWR SEG18 LCD segment output SEG18 to SEG20 and bus control signals AS RD HWR LCD segment output SEG18 to SEG20 and I O port PF3 LWR ADTRG IRQ3 Bus control signal LWR and ADTRG IRQ3 input Input port and ADTRG IRQ3 input PF2 WAIT SEG17 If WAITE 0 following reset LCD segment output SEG17 and input port If WAITE 1 LCD segment output SEG17 and WAIT input LC...

Page 249: ... Port 1 8 bit I O port Schmitt triggered input P16 P14 P17 PO15 TIOCB2 TCLKD P16 PO14 TIOCA2 IRQ1 P15 PO13 TIOCB1 TCLKC P14 PO12 TIOCA1 IRQ0 P13 PO11 TIOCD0 TCLKB P12 PO10 TIOCC0 TCLKA P11 PO9 TIOCB0 P10 PO8 TIOCA0 TPU I O pins TCLKA TCLKB TCLKC TCLKD TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 PPG output pins PO15 to PO8 and interrupt input pins IRQ0 IRQ1 and 8 bit I O port Port 2 8 b...

Page 250: ...t input port Port 5 3 bit I O port P52 SCK2 P51 RxD2 P50 TxD2 SCI channel 2 I O pins SCK2 RxD2 TxD2 and 3 bit I O port Port 9 8 bit input port P97 P96 P95 P94 P93 AN11 P92 AN10 P91 AN9 P90 AN8 A D converter analog input AN11 to AN8 and 8 bit input port Port A 8 bit I O port Built in MOS input pull up Open drain output capability PA7 A23 SEG40 PA6 A22 SEG39 PA5 A21 SEG38 PA4 A20 SEG37 PA3 A19 COM4 ...

Page 251: ...s output A7 to A0 LCD segment output SEG17 to SEG24 address output A7 to A0 and 8 bit I O port LCD segment output SEG17 to SEG24 and 8 bit I O port Port D 8 bit I O port Built in MOS input pull up PD7 D15 SEG16 PD6 D14 SEG15 PD5 D13 SEG14 PD4 D12 SEG13 PD3 D11 SEG12 PD2 D10 SEG11 PD1 D9 SEG10 PD0 D8 SEG9 Data bus I O LCD segment output SEG9 to SEG16 and data bus I O LCD segment output SEG17 to SEG...

Page 252: ...RG IRQ3 input PF2 WAIT SEG33 If WAITE 0 BREQUE 0 following reset LCD segment output SEG33 and I O port If WAITE 1 BREQUE 0 LCD segment output and WAIT input LCD segment output SEG33 and I O port PF0 IRQ2 IRQ2 input and I O port Port H 8 bit I O port PH7 PWM1H PH6 PWM1G PH5 PWM1F PH4 PWM1E PH3 PWM1D PH2 PWM1C PH1 PWM1B PH0 PWM1A PWM channel 1 output and 8 bit I O port Port J 8 bit I O port PJ7 PWM2...

Page 253: ...rt 1 pin functions change according to the operating mode Figure 9 1 shows the port 1 pin configuration P17 I O PO15 output TIOCB2 I O TCLKD input P16 I O PO14 output TIOCA2 I O IRQ1 input P15 I O PO13 output TIOCB1 I O TCLKC input P14 I O PO12 output TIOCA1 I O IRQ0 input P13 I O PO11 output TIOCD0 I O TCLKB input P12 I O PO10 output TIOCC0 I O TCLKA input P11 I O PO9 output TIOCB0 I O P10 I O PO...

Page 254: ...f which specify input or output for the pins of port 1 P1DDR cannot be read if it is an undefined value will be read Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin while clearing the bit to 0 makes the pin an input pin P1DDR is initialized to H 00 by a reset and in hardware standby mode It retains its prior state in software standby mode Port 1 Data Register P1DR Bit 7 6...

Page 255: ...to Writing of output data for the port 1 pins P17 to P10 must always be performed on P1DR If a port 1 read is performed while P1DDR bits are set to 1 the P1DR values are read If a port 1 read is performed while P1DDR bits are cleared to 0 the pin states are read After a reset and in hardware standby mode PORT1 contents are determined by the pin states as P1DDR and P1DR are initialized PORT1 retain...

Page 256: ...R1 and CCLR0 in TCR2 bits TPSC2 to TPSC0 in TCR0 and TCR5 bit NDER15 in NDERH and bit P17DDR TPU Channel 2 Setting Table Below 1 Table Below 2 P17DDR 0 1 1 NDER15 0 1 Pin function TIOCB2 output P17 input P17 output PO15 output TIOCB2 input 1 TCLKD input 2 Notes 1 TIOCB2 input when MD3 to MD0 B 0000 or B 01xx and IOB3 1 2 TCLKD input when the setting for either TCR0 or TCR5 is TPSC2 to TPSC0 B 111 ...

Page 257: ...Below 1 Table Below 2 P16DDR 0 1 1 NDER14 0 1 Pin function TIOCA2 output P16 input P16 output PO14 output TIOCA2 input 1 IRQ1 input TPU Channel 2 Setting 2 1 2 1 1 2 MD3 to MD0 B 0000 B 01xx B 001x B 0010 B 0011 IOA3 to IOA0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 CCLR1 CCLR0 Other than B 01 B 01 Output function Output compare output PWM mode 1 output 2 PWM ...

Page 258: ...B1 output P15 input P15 output PO13 output TIOCB1 input 1 TCLKC input 2 Notes 1 TIOCB1 input when MD3 to MD0 B 0000 or B 01xx and IOB3 to IOB0 B 10xx 2 TCLKC input when the setting for either TCR0 or TCR2 is TPSC2 to TPSC0 B 110 or when the setting for either TCR4 or TCR5 is TPSC2 to TPSC0 B 101 TCLKC input when channels 2 and 4 are set to phase counting mode TPU Channel 1 Setting 2 1 2 2 1 2 MD3 ...

Page 259: ...low 2 P14DDR 0 1 1 NDER12 0 1 Pin function TIOCA1 output P14 input P14 output PO12 output TIOCA1 input 1 IRQ0 input TPU Channel 1 Setting 2 1 2 1 1 2 MD3 to MD0 B 0000 B 01xx B 001x B 0010 B 0011 IOA3 to IOA0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 Other than B xx00 CCLR1 CCLR0 Other than B 01 B 01 Output function Output compare output PWM mode 1 output 2 PW...

Page 260: ... Below 2 P13DDR 0 1 1 NDER11 0 1 Pin function TIOCD0 output P13 input P13 output PO11 output TIOCD0 input 1 TCLKB input 2 Notes 1 TIOCD0 input when MD3 to MD0 B 0000 and IOD3 to IOD0 B 10xx 2 TCLKB input when the setting for TCR0 to TCR2 is TPSC2 to TPSC0 B 101 TCLKB input when channels 1 and 5 are set to phase counting mode TPU Channel 0 Setting 2 1 2 2 1 2 MD3 to MD0 B 0000 B 0010 B 0011 IOD3 to...

Page 261: ... input P12 output PO10 output TIOCC0 input 1 TCLKA input 2 TPU Channel 0 Setting 2 1 2 1 1 2 MD3 to MD0 B 0000 B 001x B 0010 B 0011 IOC3 to IOC0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 CCLR2 to CCLR0 Other than B 101 B 101 Output function Output compare output PWM mode 1 output 3 PWM mode 2 output x Don t care Notes 1 TIOCC0 input when MD3 to MD0 B 0000 and ...

Page 262: ...R TPU Channel 0 Setting Table Below 1 Table Below 2 P11DDR 0 1 1 NDER9 0 1 Pin function TIOCB0 output P11 input P11 output PO9 output TIOCB0 input Note TIOCB0 input when MD3 to MD0 B 0000 and IOB3 to IOB0 B 10xx TPU Channel 0 Setting 2 1 2 2 1 2 MD3 to MD0 B 0000 B 0010 B 0011 IOB3 to IOB0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 CCLR2 to CCLR0 Other than B 0...

Page 263: ...Channel 0 Setting Table Below 1 Table Below 2 P10DDR 0 1 1 NDER8 0 1 Pin function TIOCA0 output P10 input P10 output PO8 output TIOCA0 input 1 TPU Channel 0 Setting 2 1 2 1 1 2 MD3 to MD0 B 0000 B 001x B 0010 B 0011 IOA3 to IOA0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 CCLR2 to CCLR0 Other than B 001 B 001 Output function Output compare output PWM mode 1 outp...

Page 264: ...I O TIOCB5 I O I O TIOCA5 I O I O TIOCB4 I O I O TIOCA4 I O I O TIOCD3 I O I O TIOCC3 I O I O TIOCB3 I O I O TIOCA3 I O Port 2 pins Figure 9 2 Port 2 Pin Functions 9 3 2 Register Configuration Table 9 4 shows the configuration of port 3 registers Table 9 4 Port 2 Register Configuration Name Abbreviation R W Initial Value Address Port 2 data direction register P2DDR W H 00 H FE31 Port 2 data regist...

Page 265: ...andby mode Port 2 Data Register P2DR Bit 7 6 5 4 3 2 1 0 P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W P2DR is an 8 bit readable writable register that stores output data for the port 2 pins P27 to P20 P2DR is initialized to H 00 if a reset occurs and in the hardware standby mode The previous values are retained in the software st...

Page 266: ...on Method and Pin Functions P27 TIOCB5 Switches as follows according to the combinations of the TPU channel 5 setting made using bits MD3 to MD0 of TMDR5 bits IOB3 to IOB0 of TIOR5 and bits CCLR1 and CCLR0 of TCR5 as well as the P27DDR bit TPU Channel 5 Setting Table Below 1 Table Below 2 P27DDR 0 1 Pin function TIOCB5 output P27 input P27 output TIOCB5 input Note TIOCB5 input if MD3 to MD0 0 B 00...

Page 267: ...e P26DDR bit TPU Channel 5 Setting Table Below 1 Table Below 2 P26DDR 0 1 Pin function TIOCA5 output P26 input P26 output TIOCA5 input TPU Channel 5 Setting 2 1 2 1 1 2 MD3 to MD0 B 0000 B 01xx B 001x B 0010 B 0011 IOA3 to IOA0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 CCLR1 CCLR0 Other than B 01 B 01 Output function Output compare output PWM mode 1 output PWM...

Page 268: ...CCR0 of TCR4 as well as the P25DDR bit TPU Channel 4 Setting Table Below 1 Table Below 2 P25DDR 0 1 Pin function TIOCB4 output P25 input P25 output TIOCB4 input TPU Channel 4 Setting 2 1 2 2 1 2 MD3 to MD0 B 0000 B 01xx B 0010 B 0011 IOB3 to IOB0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 CCLR1 CCLR0 Other than B 10 B 10 Output function Output compare output PW...

Page 269: ...it TPU Channel 4 Setting Table Below 1 Table Below 2 P24DDR 0 1 Pin function TIOCA4 output P24 input P24 output TIOCA4 input TPU Channel 4 Setting 2 1 2 1 1 2 MD3 to MD0 B 0000 B 01xx B 001x B 0010 B 0011 IOA3 to IOA0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 Other than B xx00 CCLR1 CCLR0 Other than B 01 B 01 Output function Output compare output PWM mode 1 ou...

Page 270: ...DDR bit TPU Channel 3 Setting Table Below 1 Table Below 2 P23DDR 0 1 Pin function TIOCD3 output P23 input P23 output TIOCD3 input TPU Channel 3 Setting 2 1 2 2 1 2 MD3 to MD0 B 0000 B 001x B 0010 B 0011 IOD3 to IOD0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 Other than B xx00 Other than B xx00 CCLR2 to CCLR0 Other than B 110 B 110 Output function Output compare output PWM mode 1 output...

Page 271: ...e P22DDR bit TPU Channel 3 Setting Table Below 1 Table Below 2 P22DDR 0 1 Pin function TIOCC3 output P22 input P22 output TIOCC3 input TPU Channel 3 Setting 2 1 2 1 1 2 MD3 to MD0 B 0000 B 001x B 0010 B 0011 IOC3 to IOC0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 CCLR2 to CCLR0 Other than B 101 B 101 Output function Output compare output PWM mode 1 output PWM m...

Page 272: ... CCR0 of TCR3 as well as the P21DDR bit TPU Channel 3 Setting Table Below 1 Table Below 2 P21DDR 0 1 Pin function TIOCB3 output P21 input P21 output TIOCB3 input TPU Channel 3 Setting 2 1 2 2 1 2 MD3 to MD0 B 0000 B 0010 B 0011 IOB3 to IOB0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 CCLR2 to CCLR0 Other than B 010 B 010 Output function Output compare output PWM...

Page 273: ...e P20DDR bit TPU Channel 3 Setting Table Below 1 Table Below 2 P20DDR 0 1 Pin function TIOCA3 output P20 input P20 output TIOCA3 input TPU Channel 0 Setting 2 1 2 1 1 2 MD3 to MD0 B 0000 B 001x B 0010 B 0011 IOA3 to IOA0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 CCLR2 to CCLR0 Other than B 001 B 001 Output function Output compare output PWM mode 1 output PWM m...

Page 274: ...30 Port 3 I O I O I O SCK1 I O IRQ5 input I O RxD1 input I O TxD1 output I O SCK0 I O IRQ4 input I O RxD0 input I O TxD0 output Figure 9 3 Port 3 Pin Functions 9 4 2 Register Configuration Table 9 6 shows the configuration of port 3 registers Table 9 6 Port 3 Register Configuration Name Abbreviation R W Initial Value Address Port 3 data direction register P3DDR W H 00 H FE32 Port 3 data register P...

Page 275: ... 0 they become input P3DDR is initialized to H 00 by a reset and in hardware standby mode The previous state is maintained in software standby mode SCI is initialized so the pin state is determined by the specification of P3DDR and P3DR Port 3 Data Register P3DR 7 P37DR 0 R W Bit Initial value Read Write 6 P36DR 0 R W 5 P35DR 0 R W 4 P34DR 0 R W 3 P33DR 0 R W 2 P32DR 0 R W 1 P31DR 0 R W 0 P30DR 0 ...

Page 276: ...DDR and P3DR are initialized by a reset and in hardware standby mode so PORT3 is determined by the state of the pins The previous state is maintained in software standby mode Port 3 Open Drain Control Register P3ODR 7 P37ODR 0 R W Bit Initial value Read Write 6 P36ODR 0 R W 5 P35ODR 0 R W 4 P34ODR 0 R W 3 P33ODR 0 R W 2 P32ODR 0 R W 1 P31ODR 0 R W 0 P30ODR 0 R W P3ODR is an 8 bit readable writable...

Page 277: ...ording to the setting of the P36DDR bit P36DDR 0 1 Pin function P36 input pin P36 output pin Note When P36ODR 1 it becomes NMOS open drain output P35 SCK1 IRQ5 Switches as follows according to the combinations of the C A bit of SMR1 the CKE0 and CKE1 bits of SCR and the P35DDR bit CKE1 0 1 C A 0 1 CKE0 0 1 P35DDR 0 1 Pin function P35 input pin P35 output pin SCK1 output pin SCK1 output pin SCK1 in...

Page 278: ...0 0 1 P32DDR 0 1 Pin function P32 input pin P32 output pin SCK0 output pin SCK0 output pin SCK0 input pin IRQ4 input Note When P32ODR 1 it becomes NMOS open drain output P31 RxD0 Switches as follows according to combinations of bit RE of SCR0 and bit P31DDR RE 0 1 P31DDR 0 1 Pin function P31 input pin P31 output pin RxD0 input pin Note When P31ODR 1 it becomes NMOS open drain output P30 TxD0 Switc...

Page 279: ...s AN0 to AN7 Port 4 pin functions are the same in all operating modes Figure 9 4 shows the port 4 pin configuration P47 P46 P45 P44 P43 P42 P41 P40 input input input input input input input input AN7 input AN6 input AN5 input AN4 input AN3 input AN2 input AN1 input AN0 input Port 4 pins Port 4 Figure 9 4 Port 4 Pin Functions ...

Page 280: ...ation R W Initial Value Address Port 4 register PORT4 R Undefined H FFB3 Note Lower 16 bits of the address Port 4 Register PORT4 The pin states are always read when a port 4 read is performed Bit 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 Initial value R W R R R R R R R R Note Determined by state of pins P47 to P40 9 5 3 Pin Functions Port 4 pins also function as A D converter analog input pi...

Page 281: ...ating modes Figures 9 5 1 and 9 5 2 show the pin functions for port 5 Port 5 pins P52 P51 P50 Port 5 I O I O I O Figure 9 5 1 Port 5 Pin Functions H8S 2646 H8S 2646R H8S 2645 Port 5 pins P52 P51 P50 Port 5 I O SCK2 I O I O RxD2 input I O TxD2 output Figure 9 5 2 Port 5 Pin Functions H8S 2648 H8S 2648R H8S 2647 ...

Page 282: ...each of each of the pins in port 5 It is not possible to read it An undefined value is returned if an attempt is made to read it Setting one of the bits of P5DDR to 1 sets the corresponding pin in port 5 to output and clearing the bit to 0 sets the corresponding pin to input P5DDR is initialized to H 0 bits 2 to 0 if a reset occurs and in the hardware standby mode The previous values are retained ...

Page 283: ...DDR and P5DR are initialized if a reset occurs and in the hardware standby mode so the content of PORT5 is determined by the pin states The previous states are retained in the software standby mode 9 6 3 Pin Functions Tables 9 10 1 and 9 10 2 list the pin functions for port 5 In the H8S 2648 H8S 2648R and H8S 2647 port 5 pins also function as SCI I O pins TxD2 RxD2 and SCK2 Table 9 10 1 Port 5 Pin...

Page 284: ... 0 1 P52DDR 0 0 Pin function P52 input pin P52 output pin SCK2 output pin SCK2 output pin SCK2 input pin P51 RxD2 Switches as follows according to a combination of the RE bit in SCR of SCI2 and the P51DDR bit RE 0 1 P51DDR 0 1 Pin function P51 input pin P51 output pin RxD2 input pin P50 TxD2 Switches as follows according to a combination of the TE bit in SCR of SCI2 and the P50DDR bit TE 0 1 P50DD...

Page 285: ...r analog input pins AN8 to AN11 Port 9 pin functions are the same in all operating modes Figure 9 6 shows the port 9 pin configuration P97 P96 P95 P94 P93 P92 P91 P90 input input input input input input input input AN11 input AN10 input AN9 input AN8 input Port 9 pins Port 9 Figure 9 6 Port 9 Pin Functions ...

Page 286: ...iation R W Initial Value Address Port 9 register PORT9 R Undefined H FFB8 Note Lower 16 bits of the address Port 9 Register PORT9 The pin states are always read when a port 9 read is performed Bit 7 6 5 4 3 2 1 0 P97 P96 P95 P94 P93 P92 P91 P90 Initial value R W R R R R R R R R Note Determined by state of pins P97 to P90 9 7 3 Pin Functions Port 9 pins also function as A D converter analog input p...

Page 287: ... 2 PA0 A16 COM1 1 COM1 2 PA7 I O A23 output SEG24 1 output SEG40 2 output PA6 I O A22 output SEG23 1 output SEG39 2 output PA5 I O A21 output SEG22 1 output SEG38 2 output PA4 I O A20 output SEG21 1 output SEG37 2 output PA3 I O A19 output COM4 1 output COM4 2 output PA2 I O A18 output COM3 1 output COM3 2 output PA1 I O A17 output COM2 1 output COM2 2 output PA0 I O A16 output COM1 1 output COM1 ...

Page 288: ... mode It retains its prior state in software standby mode The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high impedance when a transition is made to software standby mode Modes 4 to 6 These function as segment pins if the values of bits SGS3 to SGS0 of LPCR the LCD driver are other than B 0000 If the value of bits SGS3 to SGS0 is B 0000 t...

Page 289: ... value R W R R R R R R R R Note Determined by state of pins PA7 to PA0 PORTA is an 8 bit read only register that shows the pin states It cannot be written to Writing of output data for the port A pins PA7 to PA0 must always be performed on PADR Reading a pin being used as an LCD driver returns an undefined value If a port A read is performed while PADDR bits are set to 1 the PADR values are read I...

Page 290: ...ndby mode It retains its prior state in software standby mode Port A Open Drain Control Register PAODR Bit 7 6 5 4 3 2 1 0 PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W PAODR is an 8 bit readable writable register that controls whether PMOS is on or off for each port A pin PA7 to PA0 When pins are not address and LCD outpu...

Page 291: ...output disabled PAnDDR 0 1 0 1 Pin function A23 to A20 output PA7 to PA4 input PA7 to PA4 output PA7 to PA4 input PA7 to PA4 output SEG24 to SEG21 output SEG40 to SEG37 output n 7 to 4 Table 9 14 PA3 to PA0 Pin Functions Pin Selection Method and Pin Functions PA3 A19 COM4 to PA0 A16 COM1 Switches as follows according to the combinations of bits SGS3 to SGS0 of LCD driver LPCR bits AE3 to AE0 of PF...

Page 292: ...in accordance with the settings in the LPCR and in DDR setting the corresponding PAPCR bit to 1 turns on the MOS input pull up for that pin The MOS input pull up function is in the off state after a reset and in hardware standby mode The prior state is retained in software standby mode Table 9 15 summarizes the MOS input pull up states Table 9 15 MOS Input Pull Up States Port A Pin States Reset Ha...

Page 293: ...I O I O I O I O I O I O A15 A14 A13 A12 A11 A10 A9 A8 output SEG16 1 output SEG32 2 output output SEG15 1 output SEG31 2 output output SEG14 1 output SEG30 2 output output SEG13 1 output SEG29 2 output output SEG12 1 output SEG28 2 output output SEG11 1 output SEG27 2 output output SEG10 1 output SEG26 2 output output SEG9 1 output SEG25 2 output Port B pins Mode 7 pins Pin functions in modes 4 to...

Page 294: ...e only register the individual bits of which specify input or output for the pins of port B PBDDR cannot be read if it is an undefined value will be read PBDDR is initialized to H 00 by a reset and in hardware standby mode It retains its prior state in software standby mode The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high impedance whe...

Page 295: ...e initialized PORTB retains its prior state in software standby mode Port B MOS Pull Up Control Register PBPCR Bit 7 6 5 4 3 2 1 0 PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W PBPCR is an 8 bit readable writable register that controls the MOS input pull up function incorporated into port B on an individual bit basis In mo...

Page 296: ...put PBODR is initialized to H 00 by a reset and in hardware standby mode It retains its prior state in software standby mode 9 9 3 Pin Functions Port B pins also function as LCD driver output pins H8S 2646 H8S 2646R H8S 2645 SEG16 to SEG9 H8S 2648 H8S 2648R H8S 2647 SEG32 to SEG25 and address bus outputs The pin functions differ between modes 4 to 6 and mode 7 Port B pin functions are shown in tab...

Page 297: ...nce with the settings of the LCD driver LPCR and DDR setting PBPCR to 1 turns on MOS input pull up The MOS input pull up function is in the off state after a reset and in hardware standby mode The prior state is retained by a manual reset or in software standby mode Table 9 18 summarizes the MOS input pull up states Table 9 18 MOS Input Pull Up States Port B Pin States Reset Hardware Standby Mode ...

Page 298: ... output output output output A7 A6 A5 A4 A3 A2 A1 A0 output SEG8 1 output SEG24 2 output output SEG7 1 output SEG23 2 output output SEG6 1 output SEG22 2 output output SEG5 1 output SEG21 2 output output SEG4 1 output SEG20 2 output output SEG3 1 output SEG19 2 output output SEG2 1 output SEG18 2 output output SEG1 1 output SEG17 2 output Pin functions in modes 4 and 5 PC7 PC6 PC5 PC4 PC3 PC2 PC1 ...

Page 299: ...te only register the individual bits of which specify input or output for the pins of port C PCDDR cannot be read if it is an undefined value will be read PCDDR is initialized to H 00 by a reset and in hardware standby mode It retains its prior state in software standby mode The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high impedance wh...

Page 300: ...dware standby mode PORTC contents are determined by the pin states as PCDDR and PCDR are initialized PORTC retains its prior state in software standby mode Port C MOS Pull Up Control Register PCPCR Bit 7 6 5 4 3 2 1 0 PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W PCPCR is an 8 bit readable writable register that controls t...

Page 301: ...tware standby mode 9 10 3 Pin Functions Port C can function as LCD segment output pins H8S 2646 H8S 2646R H8S 2645 SEG8 to SEG1 H8S 2648 H8S 2648R H8S 2647 SEG24 to SEG17 and as address bus outputs The pin functions differ in modes 4 5 6 and 7 The port C pin functions are listed in table 9 20 Table 9 20 Port C Pin Functions Setting of SGS3 to Port SEG output SGS0 H8S 2646 H8S 2646R H8S 2645 H8S 26...

Page 302: ...nd PCDDR the MOS input pull up is set to ON The MOS input pull up function is in the off state after a reset and in hardware standby mode The prior state is retained by a manual reset or in software standby mode Table 9 21 summarizes the MOS input pull up states Table 9 21 MOS Input Pull Up States Port C Pin States Reset Hardware Standby Mode Software Standby Mode In Other Operations Address outpu...

Page 303: ...PD7 D15 SEG16 PD6 D14 SEG15 PD5 D13 SEG14 PD4 D12 SEG13 PD3 D11 SEG12 PD2 D10 SEG11 PD1 D9 SEG10 PD0 D8 SEG9 Port D D15 D14 D13 D12 D11 D10 D9 D8 I O SEG16 output I O SEG15 output I O SEG14 output I O SEG13 output I O SEG12 output I O SEG11 output I O SEG10 output I O SEG9 output Port D pins Pin functions in modes 4 to 6 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 I O SEG16 output I O SEG15 output I O SEG14 o...

Page 304: ...0 0 0 0 0 0 0 0 R W W W W W W W W W PDDDR is an 8 bit write only register the individual bits of which specify input or output for the pins of port D PDDDR cannot be read if it is an undefined value will be read PDDDR is initialized to H 00 by a reset and in hardware standby mode It retains its prior state in software standby mode Port D Data Register PDDR Bit 7 6 5 4 3 2 1 0 PD7DR PD6DR PD5DR PD4...

Page 305: ...contents are determined by the pin states as PDDDR and PDDR are initialized PORTD retains its prior state in software standby mode Port D MOS Pull Up Control Register PDPCR Bit 7 6 5 4 3 2 1 0 PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W PDPCR is an 8 bit readable writable register that controls the MOS input pull up func...

Page 306: ...e operating mode and the PDDDR PD3 D11 PD2 D10 Operating mode Mode 4 to 6 Mode 7 PD1 D9 PD0 D8 PDnDDR 0 1 Pin function Data bus I O D15 to D8 PDn input PDn output n 7 to 0 Table 9 23 2 Port D Pin Functions H8S 2648 H8S 2648R H8S 2647 Pins Method of Selection and Pin Function PD7 D15 SEG9 to PD0 D8 SEG16 Setting of SGS3 to SGS0 Port SEG output Operating mode Mode 4 to 6 Mode 7 PDDDR 0 1 Pin functio...

Page 307: ...ding PDPCR bit to 1 turns on the MOS input pull up for that pin The MOS input pull up function is in the off state after a reset and in hardware standby mode The prior state is retained in software standby mode Table 9 24 summarizes the MOS input pull up states Table 9 24 MOS Input Pull Up States Port D Modes Reset Hardware Standby Mode Software Standby Mode In Other Operations 4 to 6 OFF OFF OFF ...

Page 308: ...iguration PE7 D7 SEG8 PE6 D6 SEG7 PE5 D5 SEG6 PE4 D4 SEG5 PE3 D3 SEG4 PE2 D2 SEG3 PE1 D1 SEG2 PE0 D0 SEG1 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 I O I O I O I O I O I O I O I O Port E pins Pin functions in modes 4 to 6 Pin functions in mode 7 D7 D6 D5 D4 D3 D2 D1 D0 I O SEG8 output I O SEG7 output I O SEG6 output I O SEG5 output I O SEG4 output I O SEG3 output I O SEG2 output I O SEG1 output PE7 PE6 PE5 ...

Page 309: ...0 0 0 R W W W W W W W W W PEDDR is an 8 bit write only register the individual bits of which specify input or output for the pins of port E PEDDR cannot be read if it is an undefined value will be read PEDDR is initialized to H 00 by a reset and in hardware standby mode It retains its prior state by a manual reset or in software standby mode Port E Data Register PEDR Bit 7 6 5 4 3 2 1 0 PE7DR PE6D...

Page 310: ...ode PORTE contents are determined by the pin states as PEDDR and PEDR are initialized PORTE retains its prior state in software standby mode Port E MOS Pull Up Control Register PEPCR Bit 7 6 5 4 3 2 1 0 PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W PEPCR is an 8 bit readable writable register that controls the MOS input pu...

Page 311: ...7 to PE0 output PE7 to PE0 input PE7 to PE0 output SEG1 to SEG8 output 9 12 4 MOS Input Pull Up Function Port E has a built in MOS input pull up function that can be controlled by software This MOS input pull up function can be used in modes 4 to 6 when 8 bit bus mode is selected or in mode 7 and can be specified as on or off on an individual bit basis In modes 4 to 6 with 8 bit bus mode selected ...

Page 312: ...et Hardware Standby Mode Software Standby Mode In Other Operations 7 OFF OFF ON OFF ON OFF 4 to 6 8 bit bus 16 bit bus OFF OFF Legend OFF MOS input pull up is always off ON OFF On when PEDDR 0 PEPCR 1 and the pin is not used as a segment driver otherwise off ...

Page 313: ...SEG33 PF0 IRQ2 Port F Port F pins PF7 input ø output PF6 I O AS output SEG20 output SEG36 output PF5 I O RD output SEG19 output SEG35 output PF4 I O HWR output SEG18 output SEG34 output PF3 I O LWR output ADTRG input IRQ3 input PF2 I O WAIT input SEG17 output SEG33 output PF0 I O IRQ2 input Pin functions in modes 4 to 6 PF7 I O ø output PF6 I O SEG20 output SEG36 output PF5 I O SEG19 output SEG35 ...

Page 314: ...PF0DDR Modes 4 to 6 Initial value 1 0 0 0 0 0 undefined 0 R W W W W W W W W Mode 7 Initial value 0 0 0 0 0 0 undefined 0 R W W W W W W W W PFDDR is an 8 bit write only register the individual bits of which specify input or output for the pins of port F PFDDR cannot be read if it is an undefined value will be read PFDDR is initialized by a reset and in hardware standby mode to H 80 in modes 4 to 6 ...

Page 315: ...0 Initial value undefined R W R R R R R R R Note Determined by state of pins PF7 to PF2 PF0 PORTF is an 8 bit read only register that shows the pin states It cannot be written to Writing of output data for the port F pins PF7 to PF2 PF0 must always be performed on PFDR If a port F read is performed while PFDDR bits are set to 1 the PFDR values are read If a port F read is performed while PFDDR bit...

Page 316: ...tions Pin Selection Method and Pin Functions PF7 ø Switches as follows according to bit PF7DDR PF7DDR 0 1 Pin function PF7 input ø output PF6 AS SEG20 H8S 2646 H8S 2646R H8S 2645 Switches as follows according to the operating mode and the setting of SGS3 to SGS0 and bit PF6DDR PF6 AS SEG36 H8S 2648 H8S 2648R H8S 2647 Operating Mode Modes 4 to 6 Mode 7 Setting of SGS3 to SGS0 SEG output Port SEG ou...

Page 317: ... H8S 2645 SEG19 output RD output SEG19 output PF5 input PF5 output H8S 2648 H8S 2648R H8S 2647 SEG35 output SEG35 output PF4 HWR SEG1 8 H8S 2646 H8S 2646R H8S 2645 Switches as follows according to the operating mode and the setting of SGS3 to SGS0 and bit PF4DDR PF4 HWR SEG34 H8S 2648 H8S 2648R H8S 2647 Operating Mode Modes 4 to 6 Mode 7 Setting of SGS3 to SGS0 SEG output Port SEG output Port PF4D...

Page 318: ... as an I O pin for other functions PF2 WAIT SEG1 7 H8S 2646 H8S 2646R H8S 2645 Switches as follows according to the operating mode and the setting of bits SGS3 to SGS0 the WAITE bit and bit PF2DDR PF2 WAIT SEG33 H8S 2648 H8S 2648R H8S 2647 Operating Mode Modes 4 to 6 Mode 7 Setting of SGS3 to SGS0 SEG output Port SEG output Port WAITE 0 1 1 PF2DDR 0 1 0 1 Pin function H8S 2646 H8S 2646R H8S 2645 S...

Page 319: ...E output PH3 I O PWM1D output PH2 I O PWM1C output PH1 I O PWM1B output PH0 I O PWM1A output Port H pin Port H Figure 9 13 Port H Pin Functions 9 14 2 Register Configuration Table 9 30 shows the port H register configuration Table 9 30 Port H Registers Name Abbreviation R W Initial Value Address Port H data direction register PHDDR W H 00 H FC20 Port H data register PHDR R W H 00 H FC24 Port H reg...

Page 320: ...register that stores output data for the port H pins PH7 to PH0 PHDR is initialized to H 00 by a reset and in hardware standby mode It retains its prior state in software standby mode Port H Register PORTH Bit 7 6 5 4 3 2 1 0 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 Initial value R W R R R R R R R R Note Determined by the state of PH7 to PH0 PORTH is an 8 bit read only register that shows the pin states It...

Page 321: ... control PWM timer output PH7 to PH0 input PH7 to PH0 output 9 15 Port J 9 15 1 Overview Port J is an 8 bit I O port Port J pins also function as motor control PWM timer output pins PWM2A to PWM2H Figure 9 14 shows the port J pin configuration PJ7 I O PWM2H output PJ6 I O PWM2G output PJ5 I O PWM2F output PJ4 I O PWM2E output PJ3 I O PWM2D output PJ2 I O PWM2C output PJ1 I O PWM2B output PJ0 I O P...

Page 322: ... W W W PJDDR is an 8 bit write only register the individual bits of which specify input or output for the pins of port J PJDDR cannot be read If it is an undefined value will be read PJDDR is initialized to H 00 by a reset and in hardware standby mode It retains its prior state in software standby mode Port J Data Register PJDR Bit 7 6 5 4 3 2 1 0 PJ7DR PJ6DR PJ5DR PJ4DR PJ3DR PJ2DR PJ1DR PJ0DR In...

Page 323: ...values are read If a port J read is performed while PJDDR bits are cleared to 0 the pin states are read After a reset and in hardware standby mode PORTJ contents are determined by the pin states as PJDDR and PJDR are initialized PORTJ retains its prior state in software standby mode 9 15 3 Pin Functions As shown in table 9 33 the port J pin functions can be switched bit by bit by changing the valu...

Page 324: ...re 9 15 Port K Pin Functions 9 16 2 Register Configuration Table 9 34 shows the port A register configuration Table 9 34 Port K Registers Name Abbreviation R W Initial Value Address Port K data direction register PKDDR W H 0 H FC22 Port K data register PKDR R W H 0 H FC26 Port K register PORTK R Undefined H FC2A Note Lower 16 bits of the address ...

Page 325: ...ue 0 0 Undefined Undefined Undefined Undefined Undefined Undefined R W R W R W PKDR is an 8 bit readable writable register that stores output data for the port K pins PK7 PK6 PKDR is initialized to H 00 if a reset occurs and in the hardware standby mode The previous values are retained in the software standby mode Port K Register PORTK Bit 7 6 5 4 3 2 1 0 PK7 PK6 Initial value Undefined Undefined ...

Page 326: ...ermined by the pin states The previous states are retained in the software standby mode 9 16 3 Pin Functions The function of the port K pins changes with the operating mode in accordance with the value of PKDDR as shown in table 9 35 Table 9 35 Port K Pin Functions PKDDR 0 1 Pin function PK7 PK6 input PK7 PK6 output ...

Page 327: ...ion of rising edge falling edge or both edge detection Counter clear operation Counter clearing possible by compare match or input capture Synchronous operation Multiple timer counters TCNT can be written to simultaneously Simultaneous clearing by compare match and input capture possible Register simultaneous input output possible by counter synchronous operation PWM mode Any PWM output duty can b...

Page 328: ...atic transfer of register data Block transfer 1 word data transfer and 1 byte data transfer possible by data transfer controller DTC Programmable pulse generator PPG output trigger can be generated Channel 0 to 3 compare match input capture signals can be used as PPG output trigger A D converter conversion start trigger can be generated Channel 0 to 5 compare match A input capture A signals can be...

Page 329: ... TGR2B TGR3A TGR3B TGR4A TGR4B TGR5A TGR5B General registers buffer registers TGR0C TGR0D TGR3C TGR3D I O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare ma...

Page 330: ...ure TGR2A TGR2B compare match or input capture TGR3A TGR3B compare match or input capture Interrupt sources 5 sources Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D Overflow 4 sources Compare match or input capture 1A Compare match or input capture 1B Overflow Underflow 4 sources Compare match or input capture...

Page 331: ...B2 Interrupt request signals Channel 3 Channel 4 Channel 5 Interrupt request signals Channel 0 Channel 1 Channel 2 Internal data bus PPG output trigger signal TIORL Module data bus TGI3A TGI3B TGI3C TGI3D TCI3V TGI4A TGI4B TCI4V TCI4U TGI5A TGI5B TCI5V TCI5U TGI0A TGI0B TGI0C TGI0D TCI0V TGI1A TGI1B TCI1V TCI1U TGI2A TGI2B TCI2V TCI2U Channel 3 Channel 4 Channel 5 Internal clock External clock Cha...

Page 332: ...ut output compare output PWM output pin Input capture out compare match B0 TIOCB0 I O TGR0B input capture input output compare output PWM output pin Input capture out compare match C0 TIOCC0 I O TGR0C input capture input output compare output PWM output pin Input capture out compare match D0 TIOCD0 I O TGR0D input capture input output compare output PWM output pin 1 Input capture out compare match...

Page 333: ...utput pin Input capture out compare match D3 TIOCD3 I O TGR3D input capture input output compare output PWM output pin 4 Input capture out compare match A4 TIOCA4 I O TGR4A input capture input output compare output PWM output pin Input capture out compare match B4 TIOCB4 I O TGR4B input capture input output compare output PWM output pin 5 Input capture out compare match A5 TIOCA5 I O TGR5A input c...

Page 334: ...FFFF H FF1C Timer general register 0D TGR0D R W H FFFF H FF1E 1 Timer control register 1 TCR1 R W H 00 H FF20 Timer mode register 1 TMDR1 R W H C0 H FF21 Timer I O control register 1 TIOR1 R W H 00 H FF22 Timer interrupt enable register 1 TIER1 R W H 40 H FF24 Timer status register 1 TSR1 R W 2 H C0 H FF25 Timer counter 1 TCNT1 R W H 0000 H FF26 Timer general register 1A TGR1A R W H FFFF H FF28 Ti...

Page 335: ...O control register 4 TIOR4 R W H 00 H FE92 Timer interrupt enable register 4 TIER4 R W H 40 H FE94 Timer status register 4 TSR4 R W 2 H C0 H FE95 Timer counter 4 TCNT4 R W H 0000 H FE96 Timer general register 4A TGR4A R W H FFFF H FE98 Timer general register 4B TGR4B R W H FFFF H FE9A 5 Timer control register 5 TCR5 R W H 00 H FEA0 Timer mode register 5 TMDR5 R W H C0 H FEA1 Timer I O control regi...

Page 336: ...nel 2 TCR2 Channel 4 TCR4 Channel 5 TCR5 Bit 7 6 5 4 3 2 1 0 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W The TCR registers are 8 bit registers that control the TCNT channels The TPU has six TCR registers one for each of channels 0 to 5 The TCR registers are initialized to H 00 by a reset and in hardware standby mode TCR register settings ...

Page 337: ...ared by counter clearing for another channel performing synchronous clearing synchronous operation 1 Channel Bit 7 Reserved 3 Bit 6 CCLR1 Bit 5 CCLR0 Description 1 2 4 5 0 0 0 TCNT clearing disabled Initial value 1 TCNT cleared by TGRA compare match input capture 1 0 TCNT cleared by TGRB compare match input capture 1 TCNT cleared by counter clearing for another channel performing synchronous clear...

Page 338: ...t at both edges Note Internal clock edge selection is valid when the input clock is ø 4 or slower This setting is ignored if the input clock is ø 1 or when overflow underflow of another channel is selected Bits 2 to 0 Time Prescaler 2 to 0 TPSC2 to TPSC0 These bits select the TCNT counter clock The clock source can be selected independently for each channel Table 10 4 shows the clock sources that ...

Page 339: ...ernal clock counts on ø 16 1 Internal clock counts on ø 64 1 0 0 External clock counts on TCLKA pin input 1 External clock counts on TCLKB pin input 1 0 Internal clock counts on ø 256 1 Counts on TCNT2 overflow underflow Note This setting is ignored when channel 1 is in phase counting mode Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 2 0 0 0 Internal clock counts on ø 1 Initial value 1 ...

Page 340: ...unts on ø 16 1 Internal clock counts on ø 64 1 0 0 External clock counts on TCLKA pin input 1 External clock counts on TCLKC pin input 1 0 Internal clock counts on ø 1024 1 Counts on TCNT5 overflow underflow Note This setting is ignored when channel 4 is in phase counting mode Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 5 0 0 0 Internal clock counts on ø 1 Initial value 1 Internal cloc...

Page 341: ...nel The TMDR registers are initialized to H C0 by a reset and in hardware standby mode TMDR register settings should be made only when TCNT operation is stopped Bits 7 and 6 Reserved It is always read as 1 and cannot be modified Bit 5 Buffer Operation B BFB Specifies whether TGRB is to operate in the normal way or TGRB and TGRD are to be used together for buffer operation When TGRD is used as a bu...

Page 342: ...rmally Initial value 1 TGRA and TGRC used together for buffer operation Bits 3 to 0 Modes 3 to 0 MD3 to MD0 These bits are used to set the timer operating mode Bit 3 MD3 1 Bit 2 MD2 2 Bit 1 MD1 Bit 0 MD0 Description 0 0 0 0 Normal operation Initial value 1 Reserved 1 0 PWM mode 1 1 PWM mode 2 1 0 0 Phase counting mode 1 1 Phase counting mode 2 1 0 Phase counting mode 3 1 Phase counting mode 4 1 Do...

Page 343: ...C or TGRD is designated for buffer operation this setting is invalid and the register operates as a buffer register The TIOR registers are 8 bit registers that control the TGR registers The TPU has eight TIOR registers two each for channels 0 and 3 and one each for channels 1 2 4 and 5 The TIOR registers are initialized to H 00 by a reset and in hardware standby mode Care is required since TIOR is...

Page 344: ...ch Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 output 1 output at compare match 1 Toggle output at compare match 1 0 0 1 0 1 TGR0B is input capture register Capture input source is TIOCB0 pin Input capture at rising edge Input capture at falling edge Input capture at both edges 1 Capture input source is channel 1 count clock Input captur...

Page 345: ...are match 1 0 0 1 0 1 TGR0D is input capture register 2 Capture input source is TIOCD0 pin Input capture at rising edge Input capture at falling edge Input capture at both edges 1 Capture input source is channel 1 count clock Input capture at TCNT1 count up count down 1 Don t care Notes 1 When bits TPSC2 to TPSC0 in TCR1 are set to B 000 and ø 1 is used as the TCNT1 count clock this setting is inv...

Page 346: ...ge Input capture at both edges 1 Capture input source is TGR0C compare match input capture Input capture at generation of TGR0C compare match input capture Don t care Channel Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 Description 2 0 0 0 0 TGR2B is Output disabled Initial value 1 1 0 1 output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle ou...

Page 347: ...at compare match 1 0 output 1 output at compare match 1 Toggle output at compare match 1 0 0 1 0 1 TGR3B is input capture register Capture input source is TIOCB3 pin Input capture at rising edge Input capture at falling edge Input capture at both edges 1 Capture input source is channel 4 count clock Input capture at TCNT4 count up count down 1 Don t care Note 1 When bits TPSC2 to TPSC0 in TCR4 are...

Page 348: ...are match 1 0 0 1 0 1 TGR3D is input capture register 2 Capture input source is TIOCD3 pin Input capture at rising edge Input capture at falling edge Input capture at both edges 1 Capture input source is channel 4 count clock Input capture at TCNT4 count up count down 1 Don t care Notes 1 When bits TPSC2 to TPSC0 in TCR4 are set to B 000 and ø 1 is used as the TCNT4 count clock this setting is inv...

Page 349: ...ge Input capture at both edges 1 Capture input source is TGR3C compare match input capture Input capture at generation of TGR3C compare match input capture Don t care Channel Bit 7 IOB3 Bit 6 IOB2 Bit 5 IOB1 Bit 4 IOB0 Description 5 0 0 0 0 TGR5B is Output disabled Initial value 1 1 0 1 output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle ou...

Page 350: ...nitial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 output 1 output at compare match 1 Toggle output at compare match 1 0 0 1 0 1 TGR0A is input capture register Capture input source is TIOCA0 pin Input capture at rising edge Input capture at falling edge Input capture...

Page 351: ... at compare match 1 0 output 1 output at compare match 1 Toggle output at compare match 1 0 0 1 0 1 TGR0C is input capture register 1 Capture input source is TIOCC0 pin Input capture at rising edge Input capture at falling edge Input capture at both edges 1 Capture input source is channel 1 count clock Input capture at TCNT1 count up count down Don t care Note 1 When the BFA bit in TMDR0 is set to...

Page 352: ...put capture at both edges 1 Capture input source is TGR0A compare match input capture Input capture at generation of channel 0 TGR0A compare match input capture Don t care Channel Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 Description 2 0 0 0 0 TGR2A is Output disabled Initial value 1 1 0 1 output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Togg...

Page 353: ...le output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 output 1 output at compare match 1 Toggle output at compare match 1 0 0 1 0 1 TGR3A is input capture register Capture input source is TIOCA3 pin Input capture at rising edge Input capture at falling edge Input capture at both edges 1 Capture input source is channel 4 count clock Input capture at TC...

Page 354: ... at compare match 1 0 output 1 output at compare match 1 Toggle output at compare match 1 0 0 1 0 1 TGR3C is input capture register 1 Capture input source is TIOCC3 pin Input capture at rising edge Input capture at falling edge Input capture at both edges 1 Capture input source is channel 4 count clock Input capture at TCNT4 count up count down Don t care Note 1 When the BFA bit in TMDR3 is set to...

Page 355: ...ge Input capture at both edges 1 Capture input source is TGR3A compare match input capture Input capture at generation of TGR3A compare match input capture Don t care Channel Bit 3 IOA3 Bit 2 IOA2 Bit 1 IOA1 Bit 0 IOA0 Description 5 0 0 0 0 TGR5A is Output disabled Initial value 1 1 0 1 output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle ou...

Page 356: ...TIER1 Channel 2 TIER2 Channel 4 TIER4 Channel 5 TIER5 Bit 7 6 5 4 3 2 1 0 TTGE TCIEU TCIEV TGIEB TGIEA Initial value 0 1 0 0 0 0 0 0 R W R W R W R W R W R W The TIER registers are 8 bit registers that control enabling or disabling of interrupt requests for each channel The TPU has six TIER registers one for each channel The TIER registers are initialized to H 40 by a reset and in hardware standby ...

Page 357: ...nd cannot be modified Bit 5 TCIEU Description 0 Interrupt requests TCIU by TCFU disabled Initial value 1 Interrupt requests TCIU by TCFU enabled Bit 4 Overflow Interrupt Enable TCIEV Enables or disables interrupt requests TCIV by the TCFV flag when the TCFV flag in TSR is set to 1 Bit 4 TCIEV Description 0 Interrupt requests TCIV by TCFV disabled Initial value 1 Interrupt requests TCIV by TCFV ena...

Page 358: ... TGIC by TGFC bit enabled Bit 1 TGR Interrupt Enable B TGIEB Enables or disables interrupt requests TGIB by the TGFB bit when the TGFB bit in TSR is set to 1 Bit 1 TGIEB Description 0 Interrupt requests TGIB by TGFB bit disabled Initial value 1 Interrupt requests TGIB by TGFB bit enabled Bit 0 TGR Interrupt Enable A TGIEA Enables or disables interrupt requests TGIA by the TGFA bit when the TGFA bi...

Page 359: ...Channel 1 TSR1 Channel 2 TSR2 Channel 4 TSR4 Channel 5 TSR5 Bit 7 6 5 4 3 2 1 0 TCFD TCFU TCFV TGFB TGFA Initial value 1 1 0 0 0 0 0 0 R W R R W R W R W R W Note Can only be written with 0 for flag clearing The TSR registers are 8 bit registers that indicate the status of each channel The TPU has six TSR registers one for each channel The TSR registers are initialized to H C0 by a reset and in har...

Page 360: ... has occurred when channels 1 2 4 and 5 are set to phase counting mode In channels 0 and 3 bit 5 is reserved It is always read as 0 and cannot be modified Bit 5 TCFU Description 0 Clearing condition Initial value When 0 is written to TCFU after reading TCFU 1 1 Setting condition When the TCNT value underflows changes from H 0000 to H FFFF Bit 4 Overflow Flag TCFV Status flag that indicates that TC...

Page 361: ...lue is transferred to TGRD by input capture signal while TGRD is functioning as input capture register Bit 2 Input Capture Output Compare Flag C TGFC Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3 In channels 1 2 4 and 5 bit 2 is reserved It is always read as 0 and cannot be modified Bit 2 TGFC Description 0 Clearing conditions Initial value Wh...

Page 362: ...lue is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Bit 0 Input Capture Output Compare Flag A TGFA Status flag that indicates the occurrence of TGRA input capture or compare match Bit 0 TGFA Description 0 Clearing conditions Initial value When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFA after rea...

Page 363: ...R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Note These counters can be used as up down counters only in phase counting mode or when counting overflow underflow on another channel In other cases they function as up counters The TCNT registers are 16 bit counters The TPU has six TCNT counters one for each channel The TCNT counters are initialized to H 0000 by a reset and in hardware ...

Page 364: ...are and input capture registers The TPU has 16 TGR registers four each for channels 0 and 3 and two each for channels 1 2 4 and 5 TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers The TGR registers are initialized to H FFFF by a reset and in hardware standby mode The TGR registers cannot be accessed in 8 bit units they must always be accessed as a 16 bit u...

Page 365: ... first stop the TCNT counter Bits 7 and 6 Reserved Should always be written with 0 Bits 5 to 0 Counter Start 5 to 0 CST5 to CST0 These bits select operation or stoppage for TCNT Bit n CSTn Description 0 TCNTn count operation is stopped Initial value 1 TCNTn performs count operation n 5 to 0 Note If 0 is written to the CST bit during operation with the TIOC pin designated for output the counter sto...

Page 366: ...YNC5 to SYNC0 These bits select whether operation is independent of or synchronized with other channels When synchronous operation is selected synchronous presetting of multiple channels 1 and synchronous clearing through counter clearing on another channel 2 are possible Bit n SYNCn Description 0 TCNTn operates independently TCNT presetting clearing is unrelated to other channels Initial value 1 ...

Page 367: ...it in MSTPCRA is set to 1 TPU operation stops at the end of the bus cycle and a transition is made to module stop mode Registers cannot be read or written to in module stop mode For details see section 22 5 Module Stop Mode MSTPCRA is initialized to H 3F by a reset and in hardware standby mode It is not initialized in software standby mode Bit 5 Module Stop MSTPA5 Specifies the TPU module stop mod...

Page 368: ...it access must always be used An example of 16 bit register access operation is shown in figure 10 2 Bus interface H Internal data bus L Bus master Module data bus TCNTH TCNTL Figure 10 2 16 Bit Register Access Operation Bus Master TCNT 16 Bits 10 3 2 8 Bit Registers Registers other than TCNT and TGR are 8 bit As the data bus to the CPU is 16 bits wide these registers can be read and written to in...

Page 369: ...gure 10 3 8 Bit Register Access Operation Bus Master TCR Upper 8 Bits Bus interface H Internal data bus L Module data bus TMDR Bus master Figure 10 4 8 Bit Register Access Operation Bus Master TMDR Lower 8 Bits Bus interface H Internal data bus L Module data bus TCR TMDR Bus master Figure 10 5 8 Bit Register Access Operation Bus Master TCR and TMDR 16 Bits ...

Page 370: ...mpare register When a compare match occurs the value in the buffer register for the relevant channel is transferred to TGR When TGR is an input capture register When input capture occurs the value in TCNT is transfer to TGR and the value previously held in TGR is transferred to the buffer register Cascaded Operation The channel 1 counter TCNT1 channel 2 counter TCNT2 channel 4 counter TCNT4 and ch...

Page 371: ...unt operation Periodic counter 1 2 4 3 5 Free running counter Start count operation Free running counter 5 1 2 3 4 5 Select output compare register Select the counter clock with bits TPSC2 to TPSC0 in TCR At the same time select the input clock edge with bits CKEG1 and CKEG0 in TCR For periodic counter operation select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR ...

Page 372: ...FFFF H 0000 CST bit TCFV Time Figure 10 7 Free Running Counter Operation When compare match is selected as the TCNT clearing source the TCNT counter for the relevant channel performs periodic count operation The TGR register for setting the period is designated as an output compare register and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR After the settings ...

Page 373: ...tch Figure 10 9 shows an example of the setting procedure for waveform output by compare match Select waveform output mode Output selection Set output timing Start count operation Waveform output 1 2 3 1 Select initial value 0 output or 1 output and compare match output value 0 output 1 output or toggle output by means of TIOR The set initial value is output at the TIOC pin until the first compare...

Page 374: ...0 TIOCA TIOCB Time TGRA TGRB No change No change No change No change 1 output 0 output Figure 10 10 Example of 0 Output 1 Output Operation Figure 10 11 shows an example of toggle output In this example TCNT has been designated as a periodic counter with counter clearing performed by compare match B and settings have been made so that output is toggled by both compare match A and compare match B TC...

Page 375: ...1 should not be selected as the counter input clock used for input capture input Input capture will not be generated if ø 1 is selected Example of input capture operation setting procedure Figure 10 12 shows an example of the input capture operation setting procedure Select input capture input Input selection Start count Input capture operation 1 2 1 Designate TGR as an input capture register by m...

Page 376: ...IOCA pin input capture input edge falling edge has been selected as the TIOCB pin input capture input edge and counter clearing by TGRB input capture has been designated for TCNT TCNT value H 0180 H 0000 TIOCA TGRA Time H 0010 H 0005 Counter cleared by TIOCB input falling edge H 0160 H 0005 H 0160 H 0010 TGRB H 0180 TIOCB Figure 10 13 Example of Input Capture Operation ...

Page 377: ...ing Synchronous presetting 1 2 Synchronous clearing Select counter clearing source Counter clearing 3 Start count 5 Set synchronous counter clearing Synchronous clearing 4 Start count 5 Clearing sourcegeneration channel No Yes 1 2 3 4 5 Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation When the TCNT counter of any of the channels designated for...

Page 378: ...and 2 counter clearing source Three phase PWM waveforms are output from pins TIOC0A TIOC1A and TIOC2A At this time synchronous presetting and synchronous clearing by TGR0B compare match is performed for channel 0 to 2 TCNT counters and the data set in TGR0B is used as the PWM cycle For details of PWM modes see section 10 4 6 PWM Modes TCNT0 to TCNT2 values H 0000 TIOC0A TIOC1A Time TGR0B Synchrono...

Page 379: ... buffer operation Table 10 5 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGR0A TGR0C TGR0B TGR0D 3 TGR3A TGR3C TGR3B TGR3D When TGR is an output compare register When a compare match occurs the value in the buffer register for the corresponding channel is transferred to the timer general register This operation is illustrated in figure 10 16 Buffer re...

Page 380: ...e 10 17 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure Figure 10 18 shows an example of the buffer operation setting procedure Select TGR function Buffer operation Set buffer operation Start count Buffer operation 1 2 3 1 Designate TGR as an input capture register or output compare register by means of TIOR 2 Designate TGR for buffer operation with bits BFA and BFB in...

Page 381: ... at compare match A and 0 output at compare match B As buffer operation has been set when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA This operation is repeated each time compare match A occurs For details of PWM modes see section 10 4 6 PWM Modes TCNT value TGR0B H 0000 TGR0C Time TGR0A H 0200 H 0520 ...

Page 382: ...ture has been set for TCNT and both rising and falling edges have been selected as the TIOCA pin input capture input edge As buffer operation has been set when the TCNT value is stored in TGRA upon occurrence of input capture A the value previously stored in TGRA is simultaneously transferred to TGRC TCNT value H 09FB H 0000 TGRC Time H 0532 TIOCA TGRA H 0F07 H 0532 H 0F07 H 0532 H 0F07 H 09FB Fig...

Page 383: ...the counter clock setting is invalid and the counter operates independently in phase counting mode Table 10 6 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Channels 1 and 2 TCNT1 TCNT2 Channels 4 and 5 TCNT4 TCNT5 Example of Cascaded Operation Setting Procedure Figure 10 21 shows an example of the setting procedure for cascaded operation Set cascading Cascaded operation Start count...

Page 384: ...ferred to TGR1A and the lower 16 bits to TGR2A TCNT2 clock TCNT2 H FFFF H 0000 H 0001 TIOCA1 TIOCA2 TGR1A H 03A2 TGR2A H 0000 TCNT1 clock TCNT1 H 03A1 H 03A2 Figure 10 22 Example of Cascaded Operation 1 Figure 10 23 illustrates the operation when counting upon TCNT2 overflow underflow has been set for TCNT1 and phase counting mode has been designated for channel 2 TCNT1 is incremented by TCNT2 ove...

Page 385: ... IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D The initial output value is the value set in TGRA or TGRC If the set values of paired TGRs are identical the output value does not change when a compare match occurs In PWM mode 1 a maximum 8 phase PWM output is possible PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers...

Page 386: ...B0 TGR0C TIOCC0 TIOCC0 TGR0D TIOCD0 1 TGR1A TIOCA1 TIOCA1 TGR1B TIOCB1 2 TGR2A TIOCA2 TIOCA2 TGR2B TIOCB2 3 TGR3A TIOCA3 TIOCA3 TGR3B TIOCB3 TGR3C TIOCC3 TIOCC3 TGR3D TIOCD3 4 TGR4A TIOCA4 TIOCA4 TGR4B TIOCB4 5 TGR5A TIOCA5 TIOCA5 TGR5B TIOCB5 Note In PWM mode 2 PWM output is not possible for the TGR register in which the period is set ...

Page 387: ...designate the TGR as an output compare register and select the initial value and output value 4 Set the cycle in the TGR selected in 2 and set the duty in the other the TGR 5 Select the PWM mode with bits MD3 to MD0 in TMDR 6 Set the CST bit in TSTR to 1 to start the count operation Figure 10 24 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation Figure 10 25 shows an example of P...

Page 388: ...ch is set as the TCNT clearing source and 0 is set for the initial output value and 1 for the output value of the other TGR registers TGR0A to TGR0D TGR1A to output a 5 phase PWM waveform In this case the value set in TGR1B is used as the cycle and the values set in the other TGRs as the duty TCNT value TGR1B H 0000 TIOCA0 Counter cleared by TGR1B compare match TGR1A TGR0D TGR0C TGR0B TGR0A TIOCB0...

Page 389: ...IOCA Time TGRB 100 duty TGRB rewritten TGRB rewritten TGRB rewritten Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRA H 0000 TIOCA Time TGRB 100 duty TGRB rewritten TGRB rewritten TGRB rewritten Output does not change when cycle register and duty register compare matches occur simultaneously 0 duty Figure 10 27 Example of PWM Mode Op...

Page 390: ...w occurs while TCNT is counting down the TCFU flag is set The TCFD bit in TSR is the count direction flag Reading the TCFD flag provides an indication of whether TCNT is counting up or down Table 10 8 shows the correspondence between external clock pins and channels Table 10 8 Phase Counting Mode Clock Input Pins External Clock Pins Channels A Phase B Phase When channel 1 or 5 is set to phase coun...

Page 391: ...zes the TCNT up down count conditions TCNT value Time Down count Up count TCLKA channels 1 and 5 TCLKC channels 2 and 4 TCLKB channels 1 and 5 TCLKD channels 2 and 4 Figure 10 29 Example of Phase Counting Mode 1 Operation Table 10 9 Up Down Count Conditions in Phase Counting Mode 1 TCLKA Channels 1 and 5 TCLKC Channels 2 and 4 TCLKB Channels 1 and 5 TCLKD Channels 2 and 4 Operation High level Up c...

Page 392: ... and 5 TCLKD Channels 2 and 4 Figure 10 30 Example of Phase Counting Mode 2 Operation Table 10 10 Up Down Count Conditions in Phase Counting Mode 2 TCLKA Channels 1 and 5 TCLKC Channels 2 and 4 TCLKB Channels 1 and 5 TCLKD Channels 2 and 4 Operation High level Don t care Low level Don t care Low level Don t care High level Up count High level Don t care Low level Don t care High level Don t care L...

Page 393: ...D channels 2 and 4 Down count Figure 10 31 Example of Phase Counting Mode 3 Operation Table 10 11 Up Down Count Conditions in Phase Counting Mode 3 TCLKA Channels 1 and 5 TCLKC Channels 2 and 4 TCLKB Channels 1 and 5 TCLKD Channels 2 and 4 Operation High level Don t care Low level Don t care Low level Don t care High level Up count High level Down count Low level Don t care High level Don t care L...

Page 394: ...LKD channels 2 and 4 Up count Down count TCNT value Figure 10 32 Example of Phase Counting Mode 4 Operation Table 10 12 Up Down Count Conditions in Phase Counting Mode 4 TCLKA Channels 1 and 5 TCLKC Channels 2 and 4 TCLKB Channels 1 and 5 TCLKD Channels 2 and 4 Operation High level Up count Low level Low level Don t care High level High level Down count Low level High level Don t care Low level Le...

Page 395: ...nd TGR0C are used for the compare match function and are set with the speed control period and position control period TGR0B is used for input capture with TGR0B and TGR0D operating in buffer mode The channel 1 counter input clock is designated as the TGR0B input capture source and detection of the pulse width of 2 phase encoder 4 multiplication pulses is performed TGR1A and TGR1B for channel 1 ar...

Page 396: ...od capture TGR0A speed control period TGR1B position period capture TGR0C position control period TGR0B pulse width capture TGR0D buffer operation Channel 0 TCLKA TCLKB Edge detection circuit Figure 10 33 Phase Counting Mode Application Example ...

Page 397: ... enabled or disabled individually When an interrupt request is generated the corresponding status flag in TSR is set to 1 If the corresponding enable disable bit in TIER is set to 1 at this time an interrupt is requested The interrupt request is cleared by clearing the status flag to 0 Relative channel priorities can be changed by the interrupt controller but the priority order within a channel is...

Page 398: ...ossible TCI2V TCNT2 overflow Not possible TCI2U TCNT2 underflow Not possible 3 TGI3A TGR3A input capture compare match Possible TGI3B TGR3B input capture compare match Possible TGI3C TGR3C input capture compare match Possible TGI3D TGR3D input capture compare match Possible TCI3V TCNT3 overflow Not possible 4 TGI4A TGR4A input capture compare match Possible TGI4B TGR4B input capture compare match ...

Page 399: ...errupt request is cleared by clearing the TCFU flag to 0 The TPU has four underflow interrupts one each for channels 1 2 4 and 5 10 5 2 DTC Activation DTC Activation The DTC can be activated by the TGR input capture compare match interrupt for a channel For details see section 8 Data Transfer Controller DTC A total of 16 TPU input capture compare match interrupts can be used as DTC activation sour...

Page 400: ...figure 10 35 shows TCNT count timing in external clock operation TCNT TCNT input clock Internal clock ø N 1 N N 1 N 2 Falling edge Rising edge Figure 10 34 Count Timing in Internal Clock Operation TCNT TCNT input clock External clock ø N 1 N N 1 N 2 Rising edge Falling edge Falling edge Figure 10 35 Count Timing in External Clock Operation ...

Page 401: ...are output pin After a match between TCNT and TGR the compare match signal is not generated until the TCNT input clock is generated Figure 10 36 shows output compare output timing TGR TCNT TCNT input clock ø N N N 1 Compare match signal TIOC pin Figure 10 36 Output Compare Output Timing Input Capture Signal Timing Figure 10 37 shows input capture signal timing TCNT Input capture input ø N N 1 N 2 ...

Page 402: ...rence is specified and figure 10 39 shows the timing when counter clearing by input capture occurrence is specified TCNT Counter clear signal Compare match signal ø TGR N N H 0000 Figure 10 38 Counter Clear Timing Compare Match TCNT Counter clear signal Input capture signal ø TGR N H 0000 N Figure 10 39 Counter Clear Timing Input Capture ...

Page 403: ...the timing in buffer operation TGRA TGRB Compare match signal TCNT ø TGRC TGRD n N N n n 1 Figure 10 40 Buffer Operation Timing Compare Match TGRA TGRB TCNT Input capture signal ø TGRC TGRD N n n N 1 N N N 1 Figure 10 41 Buffer Operation Timing Input Capture ...

Page 404: ...ompare Match Figure 10 42 shows the timing for setting of the TGF flag in TSR by compare match occurrence and TGI interrupt request signal timing TGR TCNT TCNT input clock ø N N N 1 Compare match signal TGF flag TGI interrupt Figure 10 42 TGI Interrupt Timing Compare Match ...

Page 405: ...Capture Figure 10 43 shows the timing for setting of the TGF flag in TSR by input capture occurrence and TGI interrupt request signal timing TGR TCNT Input capture signal ø N N TGF flag TGI interrupt Figure 10 43 TGI Interrupt Timing Input Capture ...

Page 406: ... shows the timing for setting of the TCFU flag in TSR by underflow occurrence and TCIU interrupt request signal timing Overflow signal TCNT overflow TCNT input clock ø H FFFF H 0000 TCFV flag TCIV interrupt Figure 10 44 TCIV Interrupt Setting Timing Underflow signal TCNT underflow TCNT input clock ø H 0000 H FFFF TCFU flag TCIU interrupt Figure 10 45 TCIU Interrupt Setting Timing ...

Page 407: ...aring by the CPU and figure 10 47 shows the timing for status flag clearing by the DTC Status flag Write signal Address ø TSR address Interrupt request signal TSR write cycle T1 T2 Figure 10 46 Timing for Status Flag Clearing by CPU Interrupt request signal Status flag Address ø Source address DTC read cycle T1 T2 Destination address T1 T2 DTC write cycle Figure 10 47 Timing for Status Flag Cleari...

Page 408: ...tes Figure 10 48 shows the input clock conditions in phase counting mode Overlap Phase differ ence Phase differ ence Overlap TCLKA TCLKC TCLKB TCLKD Pulse width Pulse width Pulse width Pulse width Notes Phase difference and overlap Pulse width 1 5 states or more 2 5 states or more Figure 10 48 Phase Difference Overlap and Pulse Width in Phase Counting Mode Caution on Period Setting When counter cl...

Page 409: ...he T2 state of a TCNT write cycle TCNT clearing takes precedence and the TCNT write is not performed Figure 10 49 shows the timing in this case Counter clear signal Write signal Address ø TCNT address TCNT TCNT write cycle T1 T2 N H 0000 Figure 10 49 Contention between TCNT Write and Clear Operations ...

Page 410: ...te of a TCNT write cycle the TCNT write takes precedence and TCNT is not incremented Figure 10 50 shows the timing in this case TCNT input clock Write signal Address ø TCNT address TCNT TCNT write cycle T1 T2 N M TCNT write data Figure 10 50 Contention between TCNT Write and Increment Operations ...

Page 411: ...ce and the compare match signal is inhibited A compare match does not occur even if the same value as before is written Figure 10 51 shows the timing in this case Compare match signal Write signal Address ø TGR address TCNT TGR write cycle T1 T2 N M TGR write data TGR N N 1 Inhibited Figure 10 51 Contention between TGR Write and Compare Match ...

Page 412: ...transferred to TGR by the buffer operation will be the data prior to the write Figure 10 52 shows the timing in this case Compare match signal Write signal Address ø Buffer register address Buffer register TGR write cycle T1 T2 N TGR N M Buffer register write data Figure 10 52 Contention between Buffer Register Write and Compare Match ...

Page 413: ...1 state of a TGR read cycle the data that is read will be the data after input capture transfer Figure 10 53 shows the timing in this case Input capture signal Read signal Address ø TGR address TGR TGR read cycle T1 T2 M Internal data bus X M Figure 10 53 Contention between TGR Read and Input Capture ...

Page 414: ...state of a TGR write cycle the input capture operation takes precedence and the write to TGR is not performed Figure 10 54 shows the timing in this case Input capture signal Write signal Address ø TCNT TGR write cycle T1 T2 M TGR M TGR address Figure 10 54 Contention between TGR Write and Input Capture ...

Page 415: ...e the buffer operation takes precedence and the write to the buffer register is not performed Figure 10 55 shows the timing in this case Input capture signal Write signal Address ø TCNT Buffer register write cycle T1 T2 N TGR N M M Buffer register Buffer register address Figure 10 55 Contention between Buffer Register Write and Input Capture ...

Page 416: ...TCFV TCFU flag in TSR is not set and TCNT clearing takes precedence Figure 10 56 shows the operation timing when a TGR compare match is specified as the clearing source and H FFFF is set in TGR Counter clear signal TCNT input clock ø TCNT TGF Disabled TCFV H FFFF H 0000 Figure 10 56 Contention between Overflow and Counter Clearing ...

Page 417: ... Contention between TCNT Write and Overflow Multiplexing of I O Pins In the H8S 2646 Series the TCLKA input pin is multiplexed with the TIOCC0 I O pin the TCLKB input pin with the TIOCD0 I O pin the TCLKC input pin with the TIOCB1 I O pin and the TCLKD input pin with the TIOCB2 I O pin When an external clock is input compare match output should not be performed from a multiplexed pin Interrupts an...

Page 418: ...386 ...

Page 419: ...tput trigger signals can be selected in 4 bit groups to provide up to two different 4 bit outputs Selectable output trigger signals Output trigger signals can be selected for each group from the compare match signals of four TPU channels Non overlap mode A non overlap margin can be provided between pulse outputs Can operate together with the data transfer controller DTC The compare match signals s...

Page 420: ...xt data enable register H Next data enable register L Next data register H Next data register L Output data register H Output data register L Internal data bus PMR PCR NDERH NDERL NDRH NDRL PODRH PODRL Pulse output pins group 3 Pulse output pins group 2 Pulse output pins group 1 Pulse output pins group 0 PODRH PODRL NDRH NDRL Control logic NDERH PMR NDERL PCR Figure 11 1 Block Diagram of PPG ...

Page 421: ...Name Symbol I O Function Pulse output 8 PO8 Output Group 2 pulse output Pulse output 9 PO9 Output Pulse output 10 PO10 Output Pulse output 11 PO11 Output Pulse output 12 PO12 Output Group 3 pulse output Pulse output 13 PO13 Output Pulse output 14 PO14 Output Pulse output 15 PO15 Output ...

Page 422: ...F Port 1 data direction register P1DDR W H 00 H FE30 Module stop control register A MSTPCRA R W H 3F H FDE8 Notes 1 Lower 16 bits of the address 2 Bits used for pulse output cannot be written to 3 When the same output trigger is selected for pulse output groups 2 and 3 by the PCR setting the NDRH address is H FE2C When the output triggers are different the NDRH address is H FE2E for group 2 and H ...

Page 423: ...ue is automatically transferred to the corresponding PODR bit when the TPU compare match event specified by PCR occurs updating the output value If pulse output is disabled the bit value is not transferred from NDR to PODR and the output value does not change NDERH and NDERL are each initialized to H 00 by a reset and in hardware standby mode They are not initialized in software standby mode NDERH...

Page 424: ...0 11 2 2 Output Data Registers H and L PODRH PODRL PODRH Bit 7 6 5 4 3 2 1 0 POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W PODRL Bit 7 6 5 4 3 2 1 0 POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Note A bit that has been set for pulse output by NDER is read only PODRH and PO...

Page 425: ... the same output trigger or different output triggers Same Trigger for Pulse Output Groups If pulse output groups 2 and 3 are triggered by the same compare match event the NDRH address is H FE2C The upper 4 bits belong to group 3 and the lower 4 bits to group 2 Address H FE2E consists entirely of reserved bits that cannot be modified and are always read as 1 Address H FE2C Bit 7 6 5 4 3 2 1 0 NDR1...

Page 426: ...s H FE2E are reserved bits that cannot be modified and are always read as 1 Address H FE2C Bit 7 6 5 4 3 2 1 0 NDR15 NDR14 NDR13 NDR12 Initial value 0 0 0 0 1 1 1 1 R W R W R W R W R W Address H FE2E Bit 7 6 5 4 3 2 1 0 NDR11 NDR10 NDR9 NDR8 Initial value 1 1 1 1 0 0 0 0 R W R W R W R W R W If pulse output groups 0 and 1 are triggered by different compare match event the address of the upper 4 bit...

Page 427: ... 8 bit readable writable register that selects output trigger signals for PPG outputs on a group by group basis PCR is initialized to H FF by a reset and in hardware standby mode It is not initialized in software standby mode Bits 7 and 6 Group 3 Compare Match Select 1 and 0 G3CMS1 G3CMS0 These bits select the compare match that triggers pulse output group 3 pins PO15 to PO12 Description Bit 7 G3C...

Page 428: ... Series has no output pins corresponding to pulse output group 1 Description Bit 3 G1CMS1 Bit 2 G1CMS0 Output Trigger for Pulse Output Group 1 0 0 Compare match in TPU channel 0 1 Compare match in TPU channel 1 1 0 Compare match in TPU channel 2 1 Compare match in TPU channel 3 Initial value Bits 1 and 0 Group 0 Compare Match Select 1 and 0 G0CMS1 G0CMS0 These bits select the compare match that tr...

Page 429: ... is initialized to H F0 by a reset and in hardware standby mode It is not initialized in software standby mode Bit 7 Group 3 Inversion G3INV Selects direct output or inverted output for pulse output group 3 pins PO15 to PO12 Bit 7 G3INV Description 0 Inverted output for pulse output group 3 low level output at pin for a 1 in PODRH 1 Direct output for pulse output group 3 high level output at pin f...

Page 430: ...L 1 Direct output for pulse output group 0 high level output at pin for a 1 in PODRL Initial value Bit 3 Group 3 Non Overlap G3NOV Selects normal or non overlapping operation for pulse output group 3 pins PO15 to PO12 Bit 3 G3NOV Description 0 Normal operation in pulse output group 3 output values updated at compare match A in the selected TPU channel Initial value 1 Non overlapping operation in p...

Page 431: ...in pulse output group 1 independent 1 and 0 output at compare match A or B in the selected TPU channel Bit 0 Group 0 Non Overlap G0NOV Selects normal or non overlapping operation for pulse output group 0 pins PO3 to PO0 However the H8S 2646 Series has no pins corresponding to pulse output group 0 Bit 0 G0NOV Description 0 Normal operation in pulse output group 0 output values updated at compare ma...

Page 432: ...A6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value 0 0 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W MSTPCRA is a 16 bit readable writable register that performs module stop mode control When the MSTPA3 bit in MSTPCRA is set to 1 PPG operation stops at the end of the bus cycle and a transition is made to module stop mode Registers cannot be read or written to in module stop mode For deta...

Page 433: ...ons Output trigger signal Pulse output pin Internal data bus Normal output inverted output C PODR Q D NDER Q NDR Q D DDR Figure 11 2 PPG Output Operation Table 11 3 PPG Operating Conditions NDER DDR Pin Function 0 0 Generic input port 1 Generic output port 1 0 Generic input port but the PODR bit is a read only bit and when compare match occurs the NDR bit value is transferred to the PODR bit 1 PPG...

Page 434: ...he specified compare match event occurs Figure 11 3 shows the timing of these operations for the case of normal output in groups 2 and 3 triggered by compare match A TCNT N N 1 ø TGRA N Compare match A signal NDRH m n PODRH PO8 to PO15 n m n Figure 11 3 Timing of Transfer and Output of NDR Contents Example ...

Page 435: ...put compare register with output disabled 2 Set the PPG output trigger period 3 Select the counter clock source with bits TPSC2 to TPSC0 in TCR Select the counter clear source with bits CCLR1 and CCLR0 4 Enable the TGIA interrupt in TIER The DTC can also be set up to transfer data to NDR 5 Set the initial output values in PODR 6 Set the DDR and NDER bits for the pins to be used for pulse output to...

Page 436: ...the TGIEA bit in TIER to 1 to enable the compare match A TGIA interrupt 2 Write H F8 in P1DDR and NDERH and set the G3CMS1 G3CMS0 G2CMS1 and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger Write output data H 80 in NDRH 3 The timer counter in the TPU channel starts When compare match A occurs the NDRH contents are transferred to PO...

Page 437: ...put disabled 2 Set the pulse output trigger period in TGRB and the non overlap margin in TGRA 3 Select the counter clock source with bits TPSC2 to TPSC0 in TCR Select the counter clear source with bits CCLR1 and CCLR0 4 Enable the TGIA interrupt in TIER The DTC can also be set up to transfer data to NDR 5 Set the initial output values in PODR 6 Set the DDR and NDER bits for the pins to be used for...

Page 438: ...ample in which pulse output is used for four phase complementary non overlapping pulse output TCNT value TCNT TGRB TGRA H 0000 NDRH 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65 PODRH PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Time Non overlap margin Figure 11 7 Non Overlapping Pulse Output Example Four Phase Complementary ...

Page 439: ...rigger Set the G3NOV and G2NOV bits in PMR to 1 to select non overlapping output Write output data H 95 in NDRH 3 The timer counter in the TPU channel starts When a compare match with TGRB occurs outputs change from 1 to 0 When a compare match with TGRA occurs outputs change from 0 to 1 the change from 0 to 1 is delayed by the value set in TGRA The TGIA interrupt handling routine writes the next o...

Page 440: ...f the PODR contents can be output Figure 11 8 shows the outputs when G3INV and G2INV are cleared to 0 in addition to the settings of figure 11 7 TCNT value TCNT TGRB TGRA H 0000 NDRH 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65 PODRL PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Time Figure 11 8 Inverted Pulse Output Example ...

Page 441: ...by compare match If TGRA functions as an input capture register in the TPU channel selected by PCR pulse output will be triggered by the input capture signal Figure 11 9 shows the timing of this output ø N M N TIOC pin Input capture signal NDR PODR M N PO Figure 11 9 Pulse Output Triggered by Input Capture Example ...

Page 442: ...ons in which the output trigger event will not occur Note on Non Overlapping Output During non overlapping operation the transfer of NDR bit values to PODR bits takes place as follows NDR bits are always transferred to PODR bits at compare match A At compare match B NDR bits are transferred only if their value is 0 Bits are not transferred if their value is 1 Figure 11 10 illustrates the non overl...

Page 443: ...upt handling routine write the next data in NDR or by having the TGIA interrupt activate the DTC Note however that the next data must be written before the next compare match B occurs Figure 11 11 shows the timing of this operation 0 1 output 0 output 0 1 output 0 output Do not write to NDR here Write to NDR here Compare match A Compare match B NDR PODR Do not write to NDR here Write to NDR here W...

Page 444: ...412 ...

Page 445: ...s 12 1 1 Features WDT features are listed below Switchable between watchdog timer mode and interval timer mode An internal reset can be issued if the timer counter overflows In the watchdog timer mode the WDT can generate an internal reset Interrupt generation when in interval timer mode If the counter overflows the WDT generates an interval timer interrupt WDT0 and WDT1 respectively allow eight a...

Page 446: ...set control RSTCSR TCNT TSCR ø 2 ø 64 ø 128 ø 512 ø 2048 ø 8192 ø 32768 ø 131072 Clock Clock select Internal clock sources Bus interface Module bus Legend TCSR TCNT RSTCSR Note Timer control status register Timer counter Reset control status register Internal bus WDT The type of internal reset signal depends on a register setting Figure 12 1 a Block Diagram of WDT0 ...

Page 447: ...ø 131072 Clock Clock select Internal clock Bus interface Internal bus Module bus TCSR TCNT Note An internal reset signal can be generated by setting the register Timer control status register Timer counter WDT Legend Internal NMI Interrupt request signal øSUB 2 øSUB 4 øSUB 8 øSUB 16 øSUB 32 øSUB 64 øSUB 128 øSUB 256 Figure 12 1 b Block Diagram of WDT1 ...

Page 448: ...on R W Initial Value Write 2 Read 0 Timer control status register 0 TCSR0 R W 3 H 18 H FF74 H FF74 Timer counter 0 TCNT0 R W H 00 H FF74 H FF75 Reset control status register RSTCSR0 R W 3 H 1F H FF76 H FF77 1 Timer control status register 1 TCSR1 R W 3 H 00 H FFA2 H FFA2 Timer counter 1 TCNT1 R W H 00 H FFA2 H FFA3 Notes 1 Lower 16 bits of the address 2 For details of write operations see section ...

Page 449: ...by the WT IT bit in TCSR TCNT is initialized to H 00 by a reset in hardware standby mode or when the TME bit is cleared to 0 It is not initialized in software standby mode Note TCNT is write protected by a password to prevent accidental overwriting For details see section 12 2 4 Notes on Register Access 12 2 2 Timer Control Status Register TCSR TCSR0 Bit 7 6 5 4 3 2 1 0 OVF WT IT TME CKS2 CKS1 CKS...

Page 450: ...ed in the interval timer interrupt service routine by reading TCSR while OVF 1 then writing 0 to OVF in accordance with the OVF flag clearing conditions However if conflict occurs between the OVF flag setting timing and OVF flag read timing when interval timer interrupts are disabled and the OVF flag is polled it has been found that in some cases the read of OVF 1 is not recognized In this case th...

Page 451: ... value 1 Watchdog timer mode WDT1 requests a reset or an NMI interrupt from the CPU when the TCNT overflows Bit 5 Timer Enable TME Selects whether TCNT runs or is halted Bit 5 TME Description 0 TCNT is initialized to H 00 and halted Initial value 1 TCNT counts WDT0 TCSR Bit 4 Reserved Bit It is always read as 1 and cannot be modified WDT1 TCSR Bit 4 Prescaler Select PSS This bit is used to select ...

Page 452: ...ct 2 to 0 CKS2 to CKS0 These bits select one of eight internal clock sources obtained by dividing the system clock ø or subclock ø SUB for input to TCNT WDT0 Input Clock Select Description Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Clock Overflow Period where ø 20 MHz 0 0 0 ø 2 initial value 25 6 µs 1 ø 64 819 2 µs 1 0 ø 128 1 6 ms 1 ø 512 6 6 ms 1 0 0 ø 2048 26 2 ms 1 ø 8192 104 9 ms 1 0 ø 32768 419 4 ms 1...

Page 453: ... 1 0 ø 128 1 6 ms 1 ø 512 6 6 ms 1 0 0 ø 2048 26 2 ms 1 ø 8192 104 9 ms 1 0 ø 32768 419 4 ms 1 ø 131072 1 68 s 1 0 0 0 øSUB 2 15 6 ms 1 øSUB 4 31 3 ms 1 0 øSUB 8 62 5 ms 1 øSUB 16 125 ms 1 0 0 øSUB 32 250 ms 1 øSUB 64 500 ms 1 0 øSUB 128 1 s 1 øSUB 256 2 s Note An overflow period is the time interval between the start of counting up from H 00 on the TCNT and the occurrence of a TCNT overflow ...

Page 454: ...cates that TCNT has overflowed changed from H FF to H 00 during watchdog timer operation This bit is not set in interval timer mode Bit 7 WOVF Description 0 Clearing condition Initial value Cleared by reading TCSR when WOVF 1 then writing 0 to WOVF 1 Setting condition Set when TCNT overflows changed from H FF to H 00 during watchdog timer operation Bit 6 Reset Enable RSTE Specifies whether or not ...

Page 455: ...ure 12 2 shows the format of data written to TCNT and TCSR TCNT and TCSR both have the same write address For a write to TCNT the upper byte of the written word must contain H 5A and the lower byte must contain the write data For a write to TCSR the upper byte of the written word must contain H A5 and the lower byte must contain the write data This transfers the write data from the lower byte to T...

Page 456: ...ars the WOVF bit to 0 but has no effect on the RSTE bits To write to the RSTE bit the upper byte must contain H 5A and the lower byte must contain the write data This writes the values in bit 6 of the lower byte into the RSTE bit but has no effect on the WOVF bit H A5 H 00 15 8 7 0 H 5A Write data 15 8 7 0 Writing 0 to WOVF bit Writing to RSTE bit Address H FF76 Address H FF76 Figure 12 3 Format o...

Page 457: ... RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0 In the case of WDT1 the chip is reset or an NMI interrupt request is generated for 516 system clock periods 516ø 515 or 516 clock periods when the clock source is øSUB PSS 1 This is illustrated in figure 12 4 b An NMI request from the watchdog timer and an interrupt request from the NMI pin are both treated as having the same v...

Page 458: ... 1 Write H 00 to TCNT 515 516 states Internal reset signal WT IT TME Legend Overflow internal reset is generated WOVF 1 Timer mode select bit Timer enable bit Note The WOVF bit is set to 1 and then cleared to 0 by an internal reset Figure 12 4 b WDT1 Watchdog Timer Operation ...

Page 459: ...H 00 Time H FF WT IT 0 TME 1 WOVI Overflow Overflow Overflow Overflow Legend WOVI Interval timer interrupt request generation WOVI WOVI WOVI Figure 12 5 Interval Timer Operation 12 3 3 Timing of Setting Overflow Flag OVF The OVF flag is set to 1 if TCNT overflows during interval timer operation At the same time an interval timer interrupt WOVI is requested This timing is shown in figure 12 6 With ...

Page 460: ...s set to 1 if TCNT overflows during watchdog timer operation If TCNT overflows while the RSTE bit in RSTCSR is set to 1 an internal reset signal is generated for the entire H8S 2646 Series chip Figure 12 7 shows the timing in this case ø TCNT H FF H 00 Overflow signal internal signal WOVF Internal reset signal 518 states WDT0 515 516 states WDT1 Figure 12 7 Timing of Setting of WOVF ...

Page 461: ...watchdog timer mode an NMI request is generated when a TCNT overflow occurs 12 5 Usage Notes 12 5 1 Contention between Timer Counter TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle the write takes priority and the timer counter is not incremented Figure 12 8 shows this operation Address ø Internal write signal TCNT input clock TCNT N M...

Page 462: ... 0 before switching the mode 12 5 4 Internal Reset in Watchdog Timer Mode In watchdog timer mode the H8S 2646 Series will not be reset internally if TCNT overflows while the RSTE bit is cleared to 0 When this module is used as a watchdog timer the RSTE bit must be set to 1 beforehand 12 5 5 OVF Flag Clearing in Interval Timer Mode When the OVF flag setting conflicts with the OVF flag reading in in...

Page 463: ...chieved character by character Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver Transmitter UART or Asynchronous Communication Interface Adapter ACIA A multiprocessor communication function is provided that enables serial data communication with a number of processors Choice of 12 serial data transfer formats Data...

Page 464: ...chronous mode 7 bit data Note Descriptions in this section refer to LSB first transfer On chip baud rate generator allows any bit rate to be selected Choice of serial clock source internal clock from baud rate generator or external clock from SCK pin Four interrupt sources Four interrupt sources transmit data empty transmit end receive data full and receive error that can issue requests independen...

Page 465: ...al data bus RxD TxD SCK Parity generation Parity check Clock External clock ø ø 4 ø 16 ø 64 TXI TEI RXI ERI SMR Legend RSR RDR TSR TDR SMR SCR SSR SCMR BRR Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Smart card mode register Bit rate register Figure 13 1 Block Diagram of SCI ...

Page 466: ...nsmit data output 1 Serial clock pin 1 SCK1 I O SCI1 clock input output Receive data pin 1 RxD1 Input SCI1 receive data input Transmit data pin 1 TxD1 Output SCI1 transmit data output 2 Serial clock pin 2 SCK2 I O SCI2 clock input output Receive data pin 2 RxD2 Input SCI2 receive data input Transmit data pin 2 TxD2 Output SCI2 transmit data output Notes Pin names SCK RxD and TxD are used in the te...

Page 467: ... W H F2 H FF7E 1 Serial mode register 1 SMR1 R W H 00 H FF80 Bit rate register 1 BRR1 R W H FF H FF81 Serial control register 1 SCR1 R W H 00 H FF82 Transmit data register 1 TDR1 R W H FF H FF83 Serial status register 1 SSR1 R W 2 H 84 H FF84 Receive data register 1 RDR1 R H 00 H FF85 Smart card mode register 1 SCMR1 R W H F2 H FF86 2 H8S 2648 Serial mode register 2 SMR2 R W H 00 H FF88 H8S 2648R ...

Page 468: ...ta Register RDR 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 0 0 R 2 0 R 1 0 R Bit Initial value R W RDR is a register that stores received serial data When the SCI has received one byte of serial data it transfers the received serial data from RSR to RDR where it is stored and completes the receive operation After this RSR is receive enabled Since RSR and RDR function as a double buffer in this way enables cont...

Page 469: ... set to 1 TSR cannot be directly read or written to by the CPU 13 2 4 Transmit Data Register TDR 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W Bit Initial value R W TDR is an 8 bit register that stores data for serial transmission When the SCI detects that TSR is empty it transfers the transmit data written in TDR to TSR and starts serial transmission Continuous serial transmissi...

Page 470: ...y mode Bit 7 Communication Mode C A Selects asynchronous mode or clocked synchronous mode as the SCI operating mode Bit 7 C A Description 0 Asynchronous mode Initial value 1 Clocked synchronous mode Bit 6 Character Length CHR Selects 7 or 8 bits as the data length in asynchronous mode In clocked synchronous mode a fixed data length of 8 bits is used regardless of the CHR setting Bit 6 CHR Descript...

Page 471: ...he O E bit setting is only valid when the PE bit is set to 1 enabling parity bit addition and checking in asynchronous mode The O E bit setting is invalid in clocked synchronous mode when parity addition and checking is disabled in asynchronous mode and when a multiprocessor format is used Bit 4 O E Description 0 Even parity 1 Initial value 1 Odd parity 2 Notes 1 When even parity is set parity bit...

Page 472: ...ter before it is sent In reception only the first stop bit is checked regardless of the STOP bit setting If the second stop bit is 1 it is treated as a stop bit if it is 0 it is treated as the start bit of the next transmit character Bit 2 Multiprocessor Mode MP Selects multiprocessor format When multiprocessor format is selected the PE bit and O E bit parity settings are invalid The MP bit settin...

Page 473: ...value R W SCR is a register that performs enabling or disabling of SCI transfer operations serial clock output in asynchronous mode and interrupt requests and selection of the serial clock source SCR can be read or written to by the CPU at all times SCR is initialized to H 00 by a reset and in standby mode Bit 7 Transmit Interrupt Enable TIE Enables or disables transmit data empty interrupt TXI re...

Page 474: ... of serial transmission by the SCI Bit 5 TE Description 0 Transmission disabled 1 Initial value 1 Transmission enabled 2 Notes 1 The TDRE flag in SSR is fixed at 1 2 In this state serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0 SMR setting must be performed to decide the transfer format before setting the TE bit to 1 Bit 4 Receive Enable...

Page 475: ...ote When receive data including MPB 0 is received receive data transfer from RSR to RDR receive error detection and setting of the RDRF FER and ORER flags in SSR is not performed When receive data including MPB 1 is received the MPB bit in SSR is set to 1 the MPIE bit is cleared to 0 automatically and generation of RXI and ERI interrupts when the TIE and RIE bits in SCR are set to 1 and FER and OR...

Page 476: ... clock source selection see table 13 9 in section 13 3 1 Overview Bit 1 Bit 0 CKE1 CKE0 Description 0 0 Asynchronous mode Internal clock SCK pin functions as I O port 1 Clocked synchronous mode Internal clock SCK pin functions as serial clock output 1 1 Asynchronous mode Internal clock SCK pin functions as clock output 2 Clocked synchronous mode Internal clock SCK pin functions as serial clock out...

Page 477: ... these flags they must be read as 1 beforehand The TEND flag and MPB flag are read only flags and cannot be modified SSR is initialized to H 84 by a reset in standby mode watch mode subactive mode and subsleep mode or module stop mode Bit 7 Transmit Data Register Empty TDRE Indicates that data has been transferred from TDR to TSR and the next serial data can be written to TDR Bit 7 TDRE Descriptio...

Page 478: ...ed while the RDRF flag is still set to 1 an overrun error will occur and the receive data will be lost Bit 5 Overrun Error ORER Indicates that an overrun error occurred during reception causing abnormal termination Bit 5 ORER Description 0 Clearing condition Initial value 1 When 0 is written to ORER after reading ORER 1 1 Setting condition When the next serial reception is completed while RDRF 1 2...

Page 479: ...annot be continued while the FER flag is set to 1 In clocked synchronous mode serial transmission cannot be continued either Bit 3 Parity Error PER Indicates that a parity error occurred during reception using parity addition in asynchronous mode causing abnormal termination Bit 3 PER Description 0 Clearing condition Initial value 1 When 0 is written to PER after reading PER 1 1 Setting condition ...

Page 480: ...B stores the multiprocessor bit in the receive data MPB is a read only bit and cannot be modified Bit 1 MPB Description 0 Clearing condition Initial value When data with a 0 multiprocessor bit is received 1 Setting condition When data with a 1 multiprocessor bit is received Note Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format Bit 0 Multiprocessor Bit Tr...

Page 481: ...mple BRR settings in asynchronous mode and table 13 4 shows sample BRR settings in clocked synchronous mode Table 13 3 BRR Settings for Various Bit Rates Asynchronous Mode ø 4 MHz ø 4 9152 MHz ø 5 MHz ø 6 MHz Bit Rate bit s n N Error n N Error n N Error n N Error 110 2 70 0 03 2 86 0 31 2 88 0 25 2 106 0 44 150 1 207 0 16 1 255 0 00 2 64 0 16 2 77 0 16 300 1 103 0 16 1 127 0 00 1 129 0 16 1 155 0 ...

Page 482: ...0 00 0 11 0 00 0 12 0 16 0 15 0 00 31250 0 5 2 40 0 7 0 00 0 9 1 70 38400 0 4 0 00 0 5 0 00 0 7 0 00 ø 10 MHz ø 12 MHz ø 12 288 MHz ø 14 MHz Bit Rate bit s n N Error n N Error n N Error n N Error 110 2 177 0 25 2 212 0 03 2 217 0 08 2 248 0 17 150 2 129 0 16 2 155 0 16 2 159 0 00 2 181 0 16 300 2 64 0 16 2 77 0 16 2 79 0 00 2 90 0 16 600 1 129 0 16 1 155 0 16 1 159 0 00 1 181 0 16 1200 1 64 0 16 1...

Page 483: ... 233 0 16 4800 0 95 0 00 0 103 0 16 0 111 0 00 0 116 0 16 9600 0 47 0 00 0 51 0 16 0 55 0 00 0 58 0 69 19200 0 23 0 00 0 25 0 16 0 27 0 00 0 28 1 02 31250 0 14 1 70 0 15 0 00 0 16 1 20 0 17 0 00 38400 0 11 0 00 0 12 0 16 0 13 0 00 0 14 2 34 ø 19 6608 MHz ø 20 MHz Bit Rate bit s n N Error n N Error 110 3 86 0 31 3 88 0 25 150 2 255 0 00 3 64 0 16 300 2 127 0 00 2 129 0 16 600 1 255 0 00 2 64 0 16 1...

Page 484: ...124 5 k 0 199 1 99 1 124 1 199 1 249 10 k 0 99 0 199 0 249 1 99 1 124 25 k 0 39 0 79 0 99 0 159 0 199 50 k 0 19 0 39 0 49 0 79 0 99 100 k 0 9 0 19 0 24 0 39 0 49 250 k 0 3 0 7 0 9 0 15 0 19 500 k 0 1 0 3 0 4 0 7 0 9 1 M 0 0 0 1 0 3 0 4 2 5 M 0 0 0 1 5 M 0 0 Note As far as possible the setting should be made so that the error is no more than 1 Legend Blank Cannot be set Can be set but there will be...

Page 485: ...bit s N BRR setting for baud rate generator 0 N 255 ø Operating frequency MHz n Baud rate generator input clock n 0 to 3 See the table below for the relation between n and the clock SMR Setting n Clock CKS1 CKS0 0 ø 0 0 1 ø 4 0 1 2 ø 16 1 0 3 ø 64 1 1 The bit rate error in asynchronous mode is found from the following formula Error ø 106 N 1 B 64 22n 1 1 100 ...

Page 486: ...Maximum Bit Rate for Each Frequency Asynchronous Mode ø MHz Maximum Bit Rate bit s n N 4 125000 0 0 4 9152 153600 0 0 5 156250 0 0 6 187500 0 0 6 144 192000 0 0 7 3728 230400 0 0 8 250000 0 0 9 8304 307200 0 0 10 312500 0 0 12 375000 0 0 12 288 384000 0 0 14 437500 0 0 14 7456 460800 0 0 16 500000 0 0 17 2032 537600 0 0 18 562500 0 0 19 6608 614400 0 0 20 625000 0 0 ...

Page 487: ...6250 12 3 0000 187500 12 288 3 0720 192000 14 3 5000 218750 14 7456 3 6864 230400 16 4 0000 250000 17 2032 4 3008 268800 18 4 5000 281250 19 6608 4 9152 307200 20 5 0000 312500 Table 13 7 Maximum Bit Rate with External Clock Input Clocked Synchronous Mode ø MHz External Input Clock MHz Maximum Bit Rate bit s 4 0 6667 666666 7 6 1 0000 1000000 0 8 1 3333 1333333 3 10 1 6667 1666666 7 12 2 0000 2000...

Page 488: ...For details of the other bits in SCMR see section 14 2 1 Smart Card Mode Register SCMR SCMR is initialized to H F2 by a reset and in standby mode Bits 7 to 4 Reserved It is always read as 1 and cannot be modified Bit 3 Smart Card Data Transfer Direction SDIR Selects the serial parallel conversion format This bit is valid when 8 bit data is used as the transmit receive format Bit 3 SDIR Description...

Page 489: ...nterface operates as a normal SCI 0 should be written in this bit Bit 0 SMIF Description 0 Operates as normal SCI smart card interface function disabled Initial value 1 Smart card interface function enabled 13 2 10 Module Stop Control Register B MSTPCRB 7 MSTPB7 1 R W 6 MSTPB6 1 R W 5 MSTPB5 1 R W 4 MSTPB4 1 R W 3 MSTPB3 1 R W 0 MSTPB0 1 R W 2 MSTPB2 1 R W 1 MSTPB1 1 R W Bit Initial value R W MSTP...

Page 490: ...it 6 Module Stop MSTPB6 Specifies the SCI1 module stop mode Bit 6 MSTPB6 Description 0 SCI1 module stop mode is cleared 1 SCI1 module stop mode is set Initial value Bit 5 Module Stop MSTPB5 Specifies the SCI2 module stop mode Bit 5 MSTPB5 Description 0 SCI2 module stop mode is cleared 1 SCI2 module stop mode is set Initial value Note H8S 2648 H8S 2648R and H8S 2647 only ...

Page 491: ... determines the transfer format and character length Detection of framing parity and overrun errors and breaks during reception Choice of internal or external clock as SCI clock source When internal clock is selected The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output When external clock is selected A clock with a frequency of 16 time...

Page 492: ... multi 8 bit data Yes No 1 bit 1 processor format 2 bits 1 0 7 bit data 1 bit 1 2 bits 1 Clocked synchronous mode 8 bit data No None Table 13 9 SMR and SCR Settings and SCI Clock Source Selection SMR SCR Setting SCI Transmit Receive Clock Bit 7 Bit 1 Bit 0 Clock C A CKE1 CKE0 Mode Source SCK Pin Function 0 0 0 Asynchronous Internal SCI does not use SCK pin 1 mode Outputs clock with same frequency ...

Page 493: ...sually held in the mark state high level The SCI monitors the transmission line and when it goes to the space state low level recognizes a start bit and starts serial communication One serial communication character consists of a start bit low level followed by data in LSB first order a parity bit high or low level and finally stop bits high level In asynchronous mode the SCI performs synchronizat...

Page 494: ...t data STOP S 8 bit data STOP STOP S 8 bit data P STOP S 7 bit data STOP P S 8 bit data MPB STOP S 8 bit data MPB STOP STOP S 7 bit data STOP MPB S 7 bit data STOP MPB STOP S 7 bit data STOP STOP CHR 0 0 0 0 1 1 1 1 0 0 1 1 MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 SMR Settings 1 2 3 4 5 6 7 8 9 10 11 12 Serial Transfer Format and Frame Length STOP S 8 bit data P STOP S 7 bit data ST...

Page 495: ...ransmit data as shown in figure 13 3 0 1 frame D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 1 Figure 13 3 Relation between Output Clock and Transfer Data Phase Asynchronous Mode Data Transfer Operations SCI initialization asynchronous mode Before transmitting and receiving data you should first clear the TE and RE bits in SCR to 0 then initialize the SCI as described below When the operating mode transfer format...

Page 496: ...k selection in SCR Be sure to clear bits RIE TIE TEIE and MPIE and bits TE and RE to 0 When the clock is selected in asynchronous mode it is output immediately after SCR settings are made 2 Set the data transfer format in SMR and SCMR 3 Write a value corresponding to the bit rate to BRR Not necessary if an external clock is used 4 Wait at least one bit interval then set the TE bit or RE bit in SCR...

Page 497: ... of 1s is output and transmission is enabled 2 SCI status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR and clear the TDRE flag to 0 3 Serial transmission continuation procedure To continue serial transmission read 1 from the TDRE flag to confirm that writing is possible then write data to TDR and then clear the TDRE flag to 0 Check...

Page 498: ...ssor bit One parity bit even or odd parity or one multiprocessor bit is output A format in which neither a parity bit nor a multiprocessor bit is output can also be selected d Stop bit s One or two 1 bits stop bits are output e Mark state 1 is output continuously until the start bit that starts the next transmission is sent 3 The SCI checks the TDRE flag at the timing for sending the stop bit If t...

Page 499: ...ity bit Stop bit Start bit Data Parity bit Stop bit TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine TEI interrupt request generated Idle state mark state TXI interrupt request generated Figure 13 6 Example of Operation in Transmission in Asynchronous Mode Example with 8 Bit Data Parity One Stop Bit ...

Page 500: ...e error After performing the appropriate error processing ensure that the ORER PER and FER flags are all cleared to 0 Reception cannot be resumed if any of these flags are set to 1 In the case of a framing error a break can be detected by reading the value of the input port corresponding to the RxD pin SCI status check and receive data read Read SSR and check that RDRF 1 then read the receive data...

Page 501: ...or processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing ORER 1 FER 1 Break PER 1 Clear RE bit in SCR to 0 Figure 13 7 Sample Serial Reception Data Flowchart cont ...

Page 502: ...ly the first is checked c Status check The SCI checks whether the RDRF flag is 0 indicating that the receive data can be transferred from RSR to RDR If all the above checks are passed the RDRF flag is set to 1 and the receive data is stored in RDR If a receive error is detected in the error check the operation is as shown in table 13 11 Note Subsequent receive operations cannot be performed when a...

Page 503: ... received data differs from the parity even or odd set in SMR Receive data is transferred from RSR to RDR Figure 13 8 shows an example of the operation for reception in asynchronous mode RDRF FER 0 1 frame D0 D1 D7 0 1 1 0 D0 D1 D7 0 1 0 1 1 Data Start bit Parity bit Stop bit Start bit Data Parity bit Stop bit RXI interrupt request generated ERI interrupt request generated by framing error Idle st...

Page 504: ...st sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added It then sends transmit data as data with a 0 multiprocessor bit added The receiving station skips the data until data with a 1 multiprocessor bit is sent When data with a 1 multiprocessor bit is received the receiving station compares that data with its own ID The ...

Page 505: ...mission to receiving station specified by ID MPB 1 MPB 0 H 01 H AA Legend MPB Multiprocessor bit Figure 13 9 Example of Inter Processor Communication Using Multiprocessor Format Transmission of Data H AA to Receiving Station A Data Transfer Operations Multiprocessor serial data transmission Figure 13 10 shows a sample flowchart for multiprocessor serial data transmission The following procedure sh...

Page 506: ... check that the TDRE flag is set to 1 then write transmit data to TDR Set the MPBT bit in SSR to 0 or 1 Finally clear the TDRE flag to 0 Serial transmission continuation procedure To continue serial transmission be sure to read 1 from the TDRE flag to confirm that writing is possible then write data to TDR and then clear the TDRE flag to 0 Checking and clearing of the TDRE flag is automatic when t...

Page 507: ...bit data is output in LSB first order c Multiprocessor bit One multiprocessor bit MPBT value is output d Stop bit s One or two 1 bits stop bits are output e Mark state 1 is output continuously until the start bit that starts the next transmission is sent 3 The SCI checks the TDRE flag at the timing for sending the stop bit If the TDRE flag is cleared to 0 data is transferred from TDR to TSR the st...

Page 508: ...erated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine TEI interrupt request generated Idle state mark state TXI interrupt request generated Figure 13 11 Example of SCI Operation in Transmission Example with 8 Bit Data Multiprocessor Bit One Stop Bit Multiprocessor serial data reception Figure 13 12 shows a sample flowchart for multiprocessor serial reception The fo...

Page 509: ...the RDRF flag is set to 1 then read the receive data in RDR and compare it with this station s ID If the data is not this station s ID set the MPIE bit to 1 again and clear the RDRF flag to 0 If the data is this station s ID clear the RDRF flag to 0 SCI status check and data reception Read SSR and check that the RDRF flag is set to 1 then read the data in RDR Receive error processing and break det...

Page 510: ... Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing Overrun error processing ORER 1 FER 1 Break Clear RE bit in SCR to 0 5 Figure 13 12 Sample Multiprocessor Serial Reception Flowchart cont ...

Page 511: ...st is not generated and RDR retains its state ID1 a Data does not match station s ID MPIE RDR value 0 D0 D1 D7 1 1 0 D0 D1 D7 0 1 1 1 Data ID2 Start bit MPB Stop bit Start bit Data Data2 MPB Stop bit RXI interrupt request multiprocessor interrupt generated MPIE 0 Idle state mark state RDRF RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine Matches this station s ID so recept...

Page 512: ...mat in Synchronous Communication In clocked synchronous serial communication data on the transmission line is output from one falling edge of the serial clock to the next Data confirmation is guaranteed at the rising edge of the serial clock In clocked serial communication one character consists of data output starting with the LSB and ending with the MSB After the MSB is output the transmission l...

Page 513: ... clearing the RE bit to 0 does not change the contents of the RDRF PER FER and ORER flags or the contents of RDR Figure 13 15 shows a sample SCI initialization flowchart Wait Transfer start Note In simultaneous transmit and receive operations the TE and RE bits should both be cleared to 0 or set to 1 simultaneously Start initialization Set data transfer format in SMR and SCMR No Yes Set value in B...

Page 514: ...The TxD pin is automatically designated as the transmit data output pin 2 SCI status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR and clear the TDRE flag to 0 3 Serial transmission continuation procedure To continue serial transmission be sure to read 1 from the TDRE flag to confirm that writing is possible then write data to TDR a...

Page 515: ...bit 7 3 The SCI checks the TDRE flag at the timing for sending the MSB bit 7 If the TDRE flag is cleared to 0 data is transferred from TDR to TSR and serial transmission of the next frame is started If the TDRE flag is set to 1 the TEND flag in SSR is set to 1 the MSB bit 7 is sent and the TxD pin maintains its state If the TEIE bit in SCR is set to 1 at this time a TEI interrupt request is genera...

Page 516: ...ng procedure should be used for serial data reception When changing the operating mode from asynchronous to clocked synchronous be sure to check that the ORER PER and FER flags are all cleared to 0 The RDRF flag will not be set if the FER or PER flag is set to 1 and neither transmit nor receive operations will be possible ...

Page 517: ...t be resumed if the ORER flag is set to 1 SCI status check and receive data read Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and clear the RDRF flag to 0 Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt Serial reception continuation procedure To continue serial reception before the MSB bit 7 of the current frame is received ...

Page 518: ... 1 when the RDRF flag changes to 1 a receive data full interrupt RXI request is generated Also if the RIE bit in SCR is set to 1 when the ORER flag changes to 1 a receive error interrupt ERI request is generated Figure 13 19 shows an example of SCI operation in reception Bit 7 Serial data Serial clock 1 frame RDRF ORER Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RXI interrupt request generated RDR data re...

Page 519: ...f a receive error occurs read the ORER flag in SSR and after performing the appropriate error processing clear the ORER flag to 0 Transmission reception cannot be resumed if the ORER flag is set to 1 SCI status check and receive data read Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and clear the RDRF flag to 0 Transition of the RDRF flag from 0 to 1 can also...

Page 520: ...pt can activate the DTC to perform data transfer The RDRF flag is cleared to 0 automatically when data transfer is performed by the DTC The DTC cannot be activated by an ERI interrupt request Table 13 12 SCI Interrupt Sources Channel Interrupt Source Description DTC Activation Priority 0 ERI Interrupt due to receive error ORER FER or PER Not possible High RXI Interrupt due to receive data full sta...

Page 521: ...is written to TDR when the TDRE flag is cleared to 0 the data stored in TDR will be lost since it has not yet been transferred to TSR It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR Operation when Multiple Receive Errors Occur Simultaneously If a number of receive errors occur at the same time the state of the status flags in SSR is as shown in...

Page 522: ...n are first set to 1 To send a break during serial transmission first clear DR to 0 then clear the TE bit to 0 When the TE bit is cleared to 0 the transmitter is initialized regardless of the current transmission state the TxD pin becomes an I O port and 0 is output from the TxD pin Receive Error Flags and Transmit Operations Clocked Synchronous Mode Only Transmission cannot be started when a rece...

Page 523: ...y formula 1 below M 0 5 1 2N L 0 5 F D 0 5 N 1 F 100 Formula 1 Where M Reception margin N Ratio of bit rate to clock N 16 D Clock duty D 0 to 1 0 L Frame length L 9 to 12 F Absolute value of clock rate deviation Assuming values of F 0 and D 0 5 in formula 1 a reception margin of 46 875 is given by formula 2 below When D 0 5 and F 0 M 0 5 1 2 16 100 46 875 Formula 2 However this is only the compute...

Page 524: ...standby mode watch mode subactive mode or subsleep mode depend on the port settings and becomes high level output after the relevant mode is cleared If a transition is made during transmission the data being transmitted will be undefined When transmitting without changing the transmit mode after the relevant mode is cleared transmission can be started by setting TE to 1 again and performing the fo...

Page 525: ...ple flowchart for mode transition during reception Read TEND flag in SSR TE 0 Transition to software standby mode etc Exit from software standby mode etc Change operating mode No All data transmitted TEND 1 Yes Yes Yes Transmission No No 1 3 2 TE 1 Initialization Start of transmission 1 Data being transmitted is interrupted After exiting software standby mode etc normal CPU transmission is possibl...

Page 526: ...om software standby Figure 13 24 Asynchronous Transmission Using Internal Clock Port input output Last TxD bit held High output Port input output Marking output Port input output SCI TxD output Port Port Note Initialized by software standby SCK output pin TE bit TxD output pin SCI TxD output Start of transmission End of transmission Transition to software standby Exit from software standby Figure ...

Page 527: ... flag in SSR Exit from software standby mode etc Change operating mode No RDRF 1 Yes Yes Reception No 1 2 RE 1 Initialization Start of reception 1 Receive data being received becomes invalid 2 Includes module stop mode Figure 13 26 Sample Flowchart for Mode Transition during Reception ...

Page 528: ...1 0 CKE0 0 and TE 1 synchronous mode low level output occurs for one half cycle 1 End of serial data transmission 2 TE bit 0 3 C A bit 0 switchover to port output 4 Occurrence of low level output see figure 13 27 SCK port Data TE C A CKE1 CKE0 Bit 7 Bit 6 1 End of transmission 4 Low level output 3 C A 0 2 TE 0 Half cycle low level output Figure 13 27 Operation when Switching from SCK Pin Function ...

Page 529: ...A 1 CKE1 0 CKE0 0 and TE 1 make the following settings in the order shown 1 End of serial data transmission 2 TE bit 0 3 CKE1 bit 1 4 C A bit 0 switchover to port output 5 CKE1 bit 0 SCK port Data TE C A CKE1 CKE0 Bit 7 Bit 6 1 End of transmission 3 CKE1 1 5 CKE1 0 4 C A 0 2 TE 0 High level output Figure 13 28 Operation when Switching from SCK Pin Function to Port Pin Function Example of Preventin...

Page 530: ...498 ...

Page 531: ...e as follows Asynchronous mode Data length 8 bits Parity bit generation and checking Transmission of error signal parity error in receive mode Error signal detection and automatic data retransmission in transmit mode Direct convention and inverse convention both supported On chip baud rate generator allows any bit rate to be selected Three interrupt sources Three interrupt sources transmit data em...

Page 532: ...tor Internal data bus RxD TxD SCK Parity generation Parity check Clock ø ø 4 ø 16 ø 64 TXI RXI ERI SMR Legend SCMR RSR RDR TSR TDR SMR SCR SSR BRR Smart Card mode register Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Figure 14 1 Block Diagram of Smart Card Interface ...

Page 533: ...put SCI0 receive data input Transmit data pin 0 TxD0 Output SCI0 transmit data output 1 Serial clock pin 1 SCK1 I O SCI1 clock input output Receive data pin 1 RxD1 Input SCI1 receive data input Transmit data pin 1 TxD1 Output SCI1 transmit data output 2 H8S 2648 Serial clock pin 2 SCK2 I O SCI2 clock input output H8S 2648R H8S 2647 Receive data pin 2 RxD2 Input SCI2 receive data input Transmit dat...

Page 534: ...e register 0 SCMR0 R W H F2 H FF7E 1 Serial mode register 1 SMR1 R W H 00 H FF80 Bit rate register 1 BRR1 R W H FF H FF81 Serial control register 1 SCR1 R W H 00 H FF82 Transmit data register 1 TDR1 R W H FF H FF83 Serial status register 1 SSR1 R W 2 H 84 H FF84 Receive data register 1 RDR1 R H 00 H FF85 Smart card mode register 1 SCMR1 R W H F2 H FF86 2 H8S 2648 Serial mode register 2 SMR2 R W H ...

Page 535: ...writable register that selects the Smart Card interface function SCMR is initialized to H F2 by a reset and in standby mode Bits 7 to 4 Reserved It is always read as 1 and cannot be modified Bit 3 Smart Card Data Transfer Direction SDIR Selects the serial parallel conversion format Bit 3 SDIR Description 0 TDR contents are transmitted LSB first Initial value Receive data is stored in RDR LSB first...

Page 536: ... Settings Bit 2 SINV Description 0 TDR contents are transmitted as they are Initial value Receive data is stored as it is in RDR 1 TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR Bit 1 Reserved It is always read as 1 and cannot be modified Bit 0 Smart Card Interface Mode Select SMIF Enables or disables the Smart Card interface function Bit 0 SMIF D...

Page 537: ...ister SSR Bit 4 Error Signal Status ERS In Smart Card interface mode bit 4 indicates the status of the error signal sent back from the receiving end in transmission Framing errors are not detected in Smart Card interface mode Bit 4 ERS Description 0 Normal reception with no error signal Clearing conditions Initial value Upon reset and in standby mode or module stop mode When 0 is written to ERS af...

Page 538: ...Upon reset and in standby mode or module stop mode When the TE bit in SCR is 0 and the ERS bit is also 0 When TDRE 1 and ERS 0 normal transmission 2 5 etu after transmission of a 1 byte serial character when GM 0 and BLK 0 When TDRE 1 and ERS 0 normal transmission 1 5 etu after transmission of a 1 byte serial character when GM 0 and BLK 1 When TDRE 1 and ERS 0 normal transmission 1 0 etu after tra...

Page 539: ... of setting of the TEND flag that indicates transmission completion is advanced and clock output control mode addition is performed The contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register SCR Bit 7 GM Description 0 Normal smart card interface mode operation Initial value TEND flag generation 12 5 etu 11 5 etu in block transfer mode after ...

Page 540: ...a retransmission not performed TXI interrupt generated by TDRE flag TEND flag set 11 5 etu after start of transmission 11 0 etu in GSM mode Note etu Elementury time unit time for transfer of 1 bit Bits 3 and 2 Basic Clock Pulse 1 and 0 BCP1 BCP0 These bits specify the number of basic clock periods in a 1 bit transfer interval on the Smart Card interface Bit 3 Bit 2 BCP1 BCP0 Description 0 1 32 clo...

Page 541: ...1 and 0 CKE1 CKE0 These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin In smart card interface mode in addition to the normal switching between clock output enabling and disabling the clock output can be specified as to be fixed high or low SCMR SMR SCR Setting SMIF C A GM CKE1 CKE0 SCK Pin Function 0 See the SCI 1 0 0 0 Operates as port I O pin 1 ...

Page 542: ...transfer mode Only asynchronous communication is supported there is no clocked synchronous communication function 14 3 2 Pin Connections Figure 14 2 shows a schematic diagram of Smart Card interface related pin connections In communication with an IC card since both transmission and reception are carried out on a single data transmission line the TxD pin and RxD pin should be connected with the LS...

Page 543: ...ent IC card Data line Clock line Reset line Figure 14 2 Schematic Diagram of Smart Card Interface Pin Connections Note If an IC card is not connected and the TE and RE bits are both set to 1 closed transmission reception is possible enabling self diagnosis to be carried out ...

Page 544: ...ng station output Start bit Data bits Parity bit Error signal Legend Ds D0 to D7 Dp DE Figure 14 3 Normal Smart Card Interface Data Format The operation sequence is as follows 1 When the data line is not in use it is in the high impedance state and is fixed high with a pull up resistor 2 The transmitting station starts transfer of one frame of data The data frame starts with a start bit Ds low lev...

Page 545: ...e in block transfer mode is as follows 1 When the data line in not in use it is in the high impedance state and is fixed high with a pull up resistor 2 The transmitting station starts transfer of one frame of data The data frame starts with a start bit Ds low level followed by 8 data bits D0 to D7 and a parity bit Dp 3 With the Smart Card interface the data line then returns to the high impedance ...

Page 546: ... O E bit is cleared to 0 if the IC card is of the direct convention type and set to 1 if of the inverse convention type Bits CKS1 and CKS0 select the clock source of the on chip baud rate generator Bits BCP1 and BCP0 select the number of basic clock periods in a 1 bit transfer interval For details see section 14 3 5 Clock The BLK bit is cleared to 0 in normal smart card interface mode and set to 1...

Page 547: ...pe the logic 1 level corresponds to state Z and the logic 0 level to state A and transfer is performed in LSB first order The start character data above is H 3B The parity bit is 1 since even parity is stipulated for the Smart Card Inverse convention SDIR SINV O E 1 Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp A Z Z A A A A A A Z Z Z State With the inverse convention type the logic 1 level corresponds to state A...

Page 548: ...determined by the bit rate and the setting of bits BCP1 and BCP0 B ø S 22n 1 N 1 106 Where N Value set in BRR 0 N 255 B Bit rate bit s ø Operating frequency MHz n See table 14 4 S Number of internal clocks in 1 bit period set by BCP1 and BCP0 Table 14 4 Correspondence between n and CKS1 CKS0 n CKS1 CKS0 0 0 0 1 1 2 1 0 3 1 Table 14 5 Examples of Bit Rate B bit s for Various BRR Settings When n 0 a...

Page 549: ... 1424 10 00 10 7136 13 00 14 2848 16 00 18 00 20 00 bit s N Error N Error N Error N Error N Error N Error N Error N Error 9600 0 0 00 1 30 1 25 1 8 99 1 0 00 1 12 01 2 15 99 2 6 60 Table 14 7 Maximum Bit Rate at Various Frequencies Smart Card Interface Mode when S 372 ø MHz Maximum Bit Rate bit s N n 7 1424 9600 0 0 10 00 13441 0 0 10 7136 14400 0 0 13 00 17473 0 0 14 2848 19200 0 0 16 00 21505 0 ...

Page 550: ...its in SMR Set the PE bit to 1 4 Set the SMIF SDIR and SINV bits in SCMR When the SMIF bit is set to 1 the TxD and RxD pins are both switched from ports to SCI pins and are placed in the high impedance state 5 Set the value corresponding to the bit rate in BRR 6 Set the CKE0 and CKE1 bits in SCR Clear the TIE RIE TE RE MPIE and TEIE bits to 0 If the CKE0 bit is set to 1 the clock is output from th...

Page 551: ...k to step 2 6 To end transmission clear the TE bit to 0 With the above processing interrupt servicing or data transfer by the DTC is possible If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled a transmit data empty interrupt TXI request will be generated If an error occurs in transmission and the ERS flag is set to 1 while the RIE bi...

Page 552: ... 0 Start transmission Start No No No Yes Yes Yes Yes No End Write data to TDR and clear TDRE flag in SSR to 0 Error processing Error processing TEND 1 All data transmitted TEND 1 ERS 0 ERS 0 Figure 14 4 Example of Transmission Processing Flow ...

Page 553: ...rmal transmission TEND flag is set In case of transmit error ERS flag is set Steps 2 and 3 above are repeated until the TEND flag is set I O signal line output Data 1 Data 1 Figure 14 5 Relation Between Transmit Operation and Internal Registers Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp I O data 12 5 etu TXI TEND interrupt 11 0 etu DE Guard time When GM 1 Legend Ds Start bit D0 to D7 Data bits Dp Parity bit DE...

Page 554: ...ther is set perform the appropriate receive error processing then clear both the ORER and the PER flag to 0 3 Repeat steps 2 and 3 until it can be confirmed that the RDRF flag is set to 1 4 Read the receive data from RDR 5 When receiving data continuously clear the RDRF flag to 0 and go back to step 2 6 To end reception clear the RE bit to 0 Initialization Read RDR and clear RDRF flag in SSR to 0 ...

Page 555: ...t confirm that the receive operation has been completed then start from initialization clearing RE bit to 0 and setting TE bit to 1 The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed When switching from transmit mode to receive mode first confirm that the transmit operation has been completed then start from initialization clearing TE bit to ...

Page 556: ...d as a DTC activation source the DTC will be activated by the TXI request and transfer of the transmit data will be carried out The TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the DTC In the event of an error the SCI retransmits the same data automatically During this period TEND remains cleared to 0 and the DTC is not activated Therefore the SCI and DTC w...

Page 557: ... the value for the fixed output state in software standby mode 2 Write 0 to the TE bit and RE bit in the serial control register SCR to halt transmit receive operation At the same time set the CKE1 bit to the value for the fixed output state in software standby mode 3 Write 0 to the CKE0 bit in SCR to halt the clock 4 Wait for one serial clock period During this interval clock output is fixed at t...

Page 558: ...Mode Data Format The data format is 8 bits with parity There is no stop bit but there is a 2 bit 1 bit or more in reception error guard time Also except during transmission with start bit data bits and parity bit the transmission pins go to the high impedance state so the signal lines must be fixed high with a pull up resistor Transmit Receive Clock Only an internal clock generated by the on chip ...

Page 559: ...ples the falling edge of the start bit using the basic clock and performs internal synchronization Receive data is latched internally at the rising edge of the 16th 32nd 186th or 128th pulse of the basic clock Figure 14 10 shows the receive data sampling timing when using a clock of 372 times the transfer rate Internal basic clock 372 clocks 186 clocks Receive data RxD Synchro nization sampling ti...

Page 560: ...ound when the received parity bit is checked the PER bit in SSR is automatically set to 1 If the RIE bit in SCR is enabled at this time an ERI interrupt request is generated The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled 2 The RDRF bit in SSR is not set for a frame in which an error has occurred 3 If no error is found when the received parity bit is checked the...

Page 561: ...ch an error signal indicating an abnormality is received 8 If an error signal is not sent back from the receiving end the ERS bit in SSR is not set 9 If an error signal is not sent back from the receiving end transmission of one frame including a retransfer is judged to have been completed and the TEND bit in SSR is set to 1 If the TIE bit in SCR is enabled at this time a TXI interrupt request is ...

Page 562: ...530 ...

Page 563: ...tion Communication speed Max 1 Mbps Data length 0 to 8 bytes Number of channels 1 Data buffers 16 one receive only buffer and 15 buffers settable for transmission reception Data transmission Choice of two methods Mailbox buffer number order low to high Message priority identifier high to low order Data reception Two methods Message identifier match transmit receive setting buffers Reception with m...

Page 564: ...Block Diagram Message Buffer Interface MBI The MBI consisting of mailboxes and a local acceptance filter mask LAFM stores CAN transmit receive messages identifiers data etc Transmit messages are written by the CPU For receive messages the data received by the CDLC is stored automatically Microprocessor Interface MPI The MPI consisting of a bus interface control register status register etc control...

Page 565: ...General status register GSR R W H 0C H F801 8 bits Bit configuration register BCR R W H 0000 H F802 8 16 bits Mailbox configuration register MBCR R W H 0100 H F804 8 16 bits Transmit wait register TXPR R W H 0000 H F806 8 16 bits Transmit wait cancel register TXCR R W H 0000 H F808 8 16 bits Transmit acknowledge register TXACK R W H 0000 H F80A 8 16 bits Abort acknowledge register ABACK R W H 0000...

Page 566: ... 1 8 MC13 1 8 R W Undefined H F888 8 16 bits Message control 14 1 8 MC14 1 8 R W Undefined H F890 8 16 bits Message control 15 1 8 MC15 1 8 R W Undefined H F898 8 16 bits Message data 0 1 8 MD0 1 8 R W Undefined H F8B0 8 16 bits Message data 1 1 8 MD1 1 8 R W Undefined H F8B8 8 16 bits Message data 2 1 8 MD2 1 8 R W Undefined H F8C0 8 16 bits Message data 3 1 8 MD3 1 8 R W Undefined H F8C8 8 16 bi...

Page 567: ...lue 1 HCAN sleep mode release by CAN bus operation enabled Bit 6 Reserved This bit always reads 0 The write value should always be 0 Bit 5 HCAN Sleep Mode MCR5 Enables or disables HCAN sleep mode transition Bit 5 MCR5 Description 0 HCAN sleep mode released Initial value 1 Transition to HCAN sleep mode enabled Bits 4 and 3 Reserved These bits always read 0 The write value should always be 0 Bit 2 M...

Page 568: ...AN reset 1 HCAN reset mode transition request Initial value In order for GSR3 to change from 1 to 0 after 0 is written to MCR0 time is required before the HCAN is internally reset There is consequently a delay before GSR3 is cleared to 0 after MCR0 is cleared to 0 15 2 2 General Status Register GSR The general status register GSR is an 8 bit readable register that indicates the status of the CAN b...

Page 569: ...eriod is the period from the start of message transmission SOF until the end of a 3 bit intermission interval after EOF End of Frame This bit cannot be written to Bit 2 GSR2 Description 0 Message transmission period 1 Reset Condition Idle period Initial value Bit 1 Transmit Receive Warning Flag GSR1 Flag that indicates an error warning This bit cannot be written to Bit 1 GSR1 Description 0 Reset c...

Page 570: ...W R W R W R W R W R W R W Bits 15 and 14 Resynchronization Jump Width SJW These bits set the bit synchronization range Bit 15 BCR7 Bit 14 BCR6 Description 0 0 Bit synchronization width 1 time quantum Initial value 1 Bit synchronization width 2 time quanta 1 0 Bit synchronization width 3 time quanta 1 Bit synchronization width 4 time quanta Bits 13 to 8 Baud Rate Prescaler BRP These bits are used t...

Page 571: ...12 Description 0 0 0 Setting prohibited Initial value 1 TSEG2 2 time quanta 1 0 TSEG2 3 time quanta 1 TSEG2 4 time quanta 1 0 0 TSEG2 5 time quanta 1 TSEG2 6 time quanta 1 0 TSEG2 7 time quanta 1 TSEG2 8 time quanta Bits 3 to 0 Time Segment 1 TSEG1 These bits are used to set the segment for absorbing output buffer CAN bus and input buffer delay A value of 1 or 4 to 16 can be set Bit 3 BCR11 Bit 2 ...

Page 572: ... R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bits 15 to 9 and 7 to 0 Mailbox Setting Register These bits set the polarity of the corresponding mailboxes Bit x MBCRx Description 0 Corresponding mailbox is set for transmission Initial value 1 Corresponding mailbox is set for re...

Page 573: ...4 3 2 1 0 TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bits 15 to 9 and 7 to 0 Transmit Wait Register These bits set a transmit wait for the corresponding mailboxes Bit x TXPRx Description 0 Transmit message idle state in corresponding mailbox Initial value Clearing condition Message transmission completion and cancellation...

Page 574: ...11 TXCR10 TXCR9 TXCR8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bits 15 to 9 and 7 to 0 Transmit Wait Cancel Register These bits control cancellation of transmit wait messages in the corresponding HCAN mailboxes Bit x TXCRx Description 0 Transmit message cancellation idle state in corresponding mailbox Initial value Clearing condition Completion of TXPR clearing when transm...

Page 575: ...5 4 3 2 1 0 TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Note Only a write of 1 is permitted to clear the flag Bits 15 to 9 and 7 to 0 Transmit Acknowledge Register These bits indicate that a transmit message in the corresponding HCAN mailbox has been transmitted normally Bit x TXACKx Description 0 Clearing conditio...

Page 576: ...5 4 3 2 1 0 ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Note Only a write of 1 is permitted to clear the flag Bits 15 to 9 and 7 to 0 Abort Acknowledge Register These bits indicate that a transmit message in the corresponding mailbox has been canceled aborted normally Bit x ABACKx Description 0 Clearing condition W...

Page 577: ...PR4 RXPR3 RXPR2 RXPR1 RXPR0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Note Only a write of 1 is permitted to clear the flag Bits 15 to 0 Receive Complete Register These bits indicate that a receive message has been received normally in ...

Page 578: ...FPR2 RFPR1 RFPR0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Note Only a write of 1 is permitted to clear the flag Bits 15 to 0 Remote Request Register These bits indicate that a remote frame has been received normally in the correspondin...

Page 579: ... R W Note Only a write of 1 is permitted to clear the flag Bit 15 Overload Frame Interrupt Flag Status flag indicating that the HCAN has transmitted an overload frame Bit 15 IRR7 Description 0 Clearing condition Writing 1 Initial value 1 Overload frame transmission Setting conditions When overload frame is transmitted Bit 14 Bus Off Interrupt Flag Status flag indicating the bus off state caused by...

Page 580: ...tting condition When REC 96 Bit 11 Transmit Overload Warning Interrupt Flag Status flag indicating the error warning state caused by the transmit error counter Bit 11 IRR3 Description 0 Clearing condition Writing 1 Initial value 1 Error warning state caused by transmit error Setting condition When TEC 96 Bit 10 Remote Frame Request Interrupt Flag Status flag indicating that a remote frame has been...

Page 581: ...de this bit executes the interrupt processing immediately by enabling an interrupt by the interrupt controller Bit 8 IRR0 Description 0 Clearing condition Writing 1 1 Hardware reset HCAN module stop software standby Initial value Setting condition When reset processing is completed after a hardware reset HCAN module stop software standby Note After reset or hardware standby release the module stop...

Page 582: ...e Setting condition When UMSR unread message status register is set Bit 0 Mailbox Empty Interrupt Flag Status flag indicating that the next transmit message can be stored in the mailbox Bit 0 IRR8 Description 0 Clearing condition Writing 1 Initial value 1 Transmit message has been transmitted or aborted and new message can be stored Setting condition When TXPR transmit wait register is cleared by ...

Page 583: ...lue 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W Bits 15 to 0 Mailbox Interrupt Mask MBIMRx Flags that enable or disable individual mailbox interrupt requests Bit x MBIMRx Description 0 Transmitting Interrupt request to CPU due to TXPR clearing ...

Page 584: ...it 15 IMR7 Description 0 Overload frame bus off recovery interrupt request to CPU by IRR7 enabled 1 Overload frame bus off recovery interrupt request to CPU by IRR7 disabled Initial value Bit 14 Bus Off Interrupt Mask Enables or disables bus off interrupt requests caused by the transmit error counter Bit 14 IMR6 Description 0 Bus off interrupt request to CPU by IRR6 enabled 1 Bus off interrupt req...

Page 585: ...eception interrupt requests Bit 10 IMR2 Description 0 Remote frame reception interrupt request to CPU by IRR2 enabled 1 Remote frame reception interrupt request to CPU by IRR2 disabled Initial value Bit 9 Receive Message Interrupt Mask Enables or disables message reception interrupt requests Bit 9 IMR1 Description 0 Message reception interrupt request to CPU by IRR1 enabled 1 Message reception int...

Page 586: ...pt request to CPU by IRR8 disabled Initial value 15 2 14 Receive Error Counter REC The receive error counter REC is an 8 bit read only register that functions as a counter indicating the number of receive message errors on the CAN bus The count value is stipulated in the CAN protocol REC Bit 7 6 5 4 3 2 1 0 Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R 15 2 15 Transmit Error Counter TEC The tr...

Page 587: ...7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Note Only 1 can be written to clear the flag Bits 15 to 0 Unread Message Status Flags UMSRx Status flags indicating that an unread receive message has...

Page 588: ... LAFML9 LAFML8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W LAFMH Bit 15 14 13 12 11 10 9 8 LAFMH7 LAFMH6 LAFMH5 LAFMH1 LAFMH0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W Bit 7 6 5 4 3 2 1 0 LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W LAFMH Bits 7 to 0 and 15 to 13 11 Bit Identifier F...

Page 589: ...eive only mailbox regardless of bit match between RX0 message identifier and receive message identifier x 15 to 0 15 2 18 Message Control MC0 to MC15 The message control register sets MC0 to MC15 consist of eight 8 bit readable writable registers MCx 1 to MCx 8 The HCAN has 16 sets of these registers MC0 to MC15 The initial value of these registers is undefined so they must be initialized by writi...

Page 590: ...D_ID4 STD_ID3 Initial value R W R W R W R W R W R W R W R W R W MCx 7 Bit 7 6 5 4 3 2 1 0 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 Initial value R W R W R W R W R W R W R W R W R W MCx 8 Bit 7 6 5 4 3 2 1 0 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 Initial value R W R W R W R W R W R W R W R W R W Undefined x 15 to 0 MCx 1 Bits 7 to 4 Reserved The...

Page 591: ...Reserved The initial value of these bits is undefined they must be initialized by writing 0 or 1 MCx 3 Bits 7 to 0 Reserved The initial value of these bits is undefined they must be initialized by writing 0 or 1 MCx 4 Bits 7 to 0 Reserved The initial value of these bits is undefined they must be initialized by writing 0 or 1 MCx 6 Bits 7 to 0 Standard Identifier STD_ID10 to STD_ID3 MCx 5 Bits 7 to...

Page 592: ...Extended format MCx 5 Bit 2 Reserved The initial value of this bit is undefined it must be initialized by writing 0 or 1 MCx 5 Bits 1 and 0 Extended Identifier EXD_ID17 EXD_ID16 MCx 8 Bits 7 to 0 Extended Identifier EXD_ID15 to EXD_ID8 MCx 7 Bits 7 to 0 Extended Identifier EXD_ID7 to EXD_ID0 These bits set the identifier extended identifier of data frames and remote frames Extended Identifier IDE ...

Page 593: ...C Bit 7 6 5 4 3 2 1 0 MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W MSTPCRC is an 8 bit readable writable register that performs module stop mode control When the MSTPC3 bit is set to 1 HCAN operation is stopped at the end of the bus cycle and module stop mode is entered Register read write accesses are not possible in mod...

Page 594: ...initialization state is not entered until the message has been completed During initialization the reset state bit GSR3 in GSR is set In this kind of initialization the error counters TEC and REC are initialized but other registers and RAM mailboxes are not A flowchart of this reset is shown in figure 15 5 15 3 2 Initialization after Hardware Reset After a hardware reset the following initializati...

Page 595: ...terrupt mask setting MC x setting receive identifier setting LAFM setting receive identifier mask setting MCR0 0 Bit configuration mode Period in which BCR MBCR etc are initialized Settings by user Processing by hardware Yes Yes No No Notes 1 When IRR0 is set to 1 automatically due to a hardware reset 2 a hardware reset initiated reset processing interrupt is generated 2 In a reset and in hardware...

Page 596: ...r Processing by hardware Yes Yes No No MCR0 0 GSR3 0 No IMR setting MBIMR setting MC x setting LAFM setting OK No Yes Yes Yes Correction Correction No BCR setting MBCR setting Mailbox RAM initialization Message transmission method initialization OK GSR3 0 11 recessive bits received Figure 15 5 Software Reset Flowchart ...

Page 597: ... the CAN bus have the same baud rate and bit width Refer to table 15 3 for the range of values that can be used as settings TSEG1 TSEG2 BRP sample point and SJW for BCR Table 15 3 BCR Register Value Setting Ranges Name Abbreviation Min Value Max Value Time segment 1 TSEG1 B 0011 B 1111 Time segment 2 TSEG2 B 001 B 111 Baud rate prescaler BRP B 000000 B 111111 Sample point SAM B 0 B 1 Re synchroniz...

Page 598: ...ay between networks PHSEG1 Buffer segment for correcting phase drift positive This segment is extended when synchronization resynchronization is established PHSEG2 Buffer segment for correcting phase drift negative This segment is shortened when synchronization resynchronization is established Note The time quanta values of TSEG1 and TSEG2 become the value of TSEG 1 Figure 15 6 Detailed Descriptio...

Page 599: ...lue other than BRP 13 8 B 000000 can be set Mailbox Transmit Receive Settings HCAN0 1 each have 16 mailboxes Mailbox 0 is receive only while mailboxes 1 to 15 can be set for transmission or reception Mailboxes that can be set for transmission or reception must be designated either for transmission use or for reception use before communication begins The Initial status of mailboxes 1 to 15 is for t...

Page 600: ...R designates the corresponding mailbox for reception use When setting mailboxes for reception to improve message transmission efficiency high priority messages should be set in low to high mailbox order priority order mailbox 1 mailbox 15 Receive only mailbox mailbox 0 No setting is necessary as this mailbox is always used for reception ...

Page 601: ...ge in the transmit buffer and message transmission is performed when the transmission right is acquired When the TXPR bit is set internal arbitration is performed again and the highest priority message is found and stored in the transmit buffer When b is selected if a number of messages are designated as waiting for transmission TXPR 1 messages are stored in the transmit buffer in low to high mail...

Page 602: ...n be set for transmission or reception mailboxes 1 to 15 To set a mailbox for transmission clear the corresponding bit to 0 in the mailbox configuration register MBCR Refer to Mailbox transmit receive settings in section 15 3 2 Initialization after Hardware Reset for details Mailbox initialization As message control data registers MCx x MDx x are configured in RAM their initial values after poweri...

Page 603: ... setting Arbitration field setting Control field setting Data field setting Message transmission wait TXPR setting Bus idle No Message transmission GSR2 0 during transmission only Transmission completed No TXACK 1 IRR8 1 IMR8 1 Yes Interrupt to CPU Clear TXACK Clear IRR8 End of transmission Settings by user Processing by hardware Yes Yes No Figure 15 7 Transmission Flowchart ...

Page 604: ... in DLC0 DLC3 The register to be set is MCx 1 Data field setting In the data field the data to be transmitted is set in byte units in the range of 0 to 8 bytes The registers to be set are MDx 1 MDx 8 The number of bytes in the data actually transmitted depends on the data length code DLC in the control field If a value exceeding the value set in DLC is set in the data field only the number of byte...

Page 605: ...upts they can issue an interrupt to the CPU Message transmission cancellation Transmission cancellation can be specified for a message stored in a mailbox as a transmit wait message A transmit wait message is canceled by setting the bit for the corresponding mailbox TXCR1 TXCR15 to 1 in the transmit cancel register TXCR When cancellation is executed the transmit wait register TXPR is automatically...

Page 606: ...essage not sent Clear TXCR TXPR ABACK 1 IRR8 1 IMR8 1 Yes Interrupt to CPU Clear TXACK Clear ABACK Clear IRR8 End of transmission transmission cancellation Completion of message transmission TXACK 1 Clear TXCR TXPR IRR8 1 Yes No Settings by user Processing by hardware Figure 15 8 Transmit Message Cancellation Flowchart ...

Page 607: ...he HCAN is in bit configuration mode IRR0 clearing The reset interrupt flag IRR0 is always set after a reset or recovery from software standby mode A HCAN interrupt is immediately entered if interrupts are enabled so the IRR0 must be cleared Bit rate settings Set values relating to the CAN bus communication speed and resynchronization Refer to Bit Rate and Bit Timing Settings in section 15 3 2 Ini...

Page 608: ...are configured in RAM their initial values after powering on are undefined and so bit initialization is necessary Write 0s or 1s to the mailboxes Refer to Mailbox message control data MCx x MDx x initial settings in section 15 3 2 Initialization after Hardware Reset for details ...

Page 609: ...d Message data read Clear IRR1 End of reception Yes No Yes No Unread message RXPR RFPR 1 IRR2 1 IRR1 1 Yes IMR2 1 Interrupt to CPU Message control read Message data read Clear all RXPRn and RFPRn bits in the mailbox which enables the receive interupt requests in the MBIMR Clear all RXPR bit in the mailbox which enables the receive interupts requests in the MBIMR Clear IRR2 IRR1 Transmission of dat...

Page 610: ...MR When receiving data frame and remote frame receive wait interrupts can be masked Interrupt register IRR interrupts can be masked in the interrupt mask register IMR Arbitration field setting In the arbitration field the identifier STD_ID0 STD_ID10 EXT_ID0 EXT_ID17 of the message to be received is set If all the bits in the set identifier do not match the message is not stored in a mailbox Exampl...

Page 611: ...IMR0 MBIMR15 in the mailbox interrupt mask register MBIMR and the receive message interrupt mask IMR1 in the interrupt mask register IMR are set to the interrupt enable value at this time an interrupt can be sent to the CPU Remote frame reception Two kinds of messages data frames and remote frames can be stored in mailboxes A remote frame differs from a data frame in that the remote reception requ...

Page 612: ...ure 15 10 shows a flowchart of unread message overwriting UMSR 1 IRR9 1 Unread message overwrite IMR9 1 End Yes Interrupt to CPU Clear IRR9 Message control message data read No Settings by user Processing by hardware Figure 15 10 Unread Message Overwrite Flowchart ...

Page 613: ...a flowchart of the HCAN sleep mode MCR5 1 Bus operation IRR12 1 Initialize TEC and REC IMR12 1 Sleep mode clearing method MCR7 0 MCR5 0 CAN bus communication possible CPU interrupt MCR5 0 Clear sleep mode Yes Yes No Yes No Yes manual No automatic No Yes Yes No Settings by user Processing by hardware 11 recessive bits No Bus idle Figure 15 11 HCAN Sleep Mode Flowchart ...

Page 614: ...ration occurs automatically when the CAN bus performs an operation and this change is detected The first message is not received in the mailbox and normal receiving starts from the next message When a change is detected on the CAN bus in HCAN sleep mode the bus operation interrupt flag IRR12 is set in the interrupt register IRR If the bus interrupt mask IMR12 in the interrupt mask register IMR is ...

Page 615: ...lemented using the mailbox interrupt mask register MBIMR and interrupt mask register IMR Table 15 5 HCAN Interrupt Sources IPR Bits Vector Vector Number IRR Bit Description IPRM 2 0 ERS0 108 IRR5 Error passive interrupt TEC 128 or REC 128 IRR6 Bus off interrupt TEC 256 OVR0 108 IRR0 Reset processing interrupt IRR2 Remote frame reception interrupt IRR3 Error warning interrupt TEC 96 IRR4 Error warn...

Page 616: ... due to a receive interrupt from the HCAN cannot be sent to the CPU in this case Figure 15 13 shows a DTC transfer flowchart DTC enable register setting DTC register information setting End of DTC transfer End No DTC initialization Message reception in HCAN s mailbox 0 DTC activation Transfer counter 0 or DISEL 1 No Interrupt to CPU Yes Yes Settings by user Processing by hardware RXPR and RFPR cle...

Page 617: ...refore mailbox initialization must always be carried out after a reset or a transition to hardware standby mode or software standby mode The reset interrupt flag IRR0 is always set after a reset or recovery from software standby mode This bit cannot be masked by the interrupt mask register IMR When a flag is not cleared and the interrupt controller enables HCAN interrupts the HCAN interrupts the C...

Page 618: ...N bus disable the HCAN by means of an error warning interrupt or by setting the HCAN module stop mode through detection of a fixed 1 state by the HxRD pin monitor 10 Transition to HCAN sleep mode The HCAN stops transmission reception stops when MCR0 is cleared to 0 immediately after an HCAN sleep mode transition effected by setting TXPR of the HCAN to 1 and setting MCR5 to 1 When a transition is m...

Page 619: ...ion time 13 3 µs per channel at 20 MHz operation Choice of single mode or scan mode Single mode Single channel A D conversion Scan mode Continuous A D conversion on 1 to 4 channels Four data registers Conversion results are held in a 16 bit data register for each channel Sample and hold function Three kinds of conversion start Choice of software or timer conversion start trigger TPU or ADTRG pin A...

Page 620: ...ce A D C S R A D C R A D D R D A D D R C A D D R B A D D R A AVCC Vref AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 ADTRG Conversion start trigger from TPU Successive approximations register Multiplexer ADCR ADCSR ADDRA ADDRB ADDRC ADDRD A D control register A D control status register A D data register A A D data register B A D data register C A D data register D Figure 16 1 Block Diagr...

Page 621: ...r Pins Pin Name Symbol I O Function Analog power supply pin AVCC Input Analog block power supply Analog ground pin AVSS Input Analog block ground and reference voltage Reference voltage pin Vref Input A D conversion reference voltage Analog input pin 0 AN0 Input Channel set 0 CH3 0 group 0 analog inputs Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog i...

Page 622: ...r BH ADDRBH R H 00 H FF92 A D data register BL ADDRBL R H 00 H FF93 A D data register CH ADDRCH R H 00 H FF94 A D data register CL ADDRCL R H 00 H FF95 A D data register DH ADDRDH R H 00 H FF96 A D data register DL ADDRDL R H 00 H FF97 A D control status register ADCSR R W 2 H 00 H FF98 A D control register ADCR R W H 33 H FF99 Module stop control register A MSTPCRA R W H 3F H FDE8 Notes 1 Lower 1...

Page 623: ...8 of ADDR and the lower 2 bits are transferred to the lower byte bits 7 and 6 and stored Bits 5 to 0 are always read as 0 The correspondence between the analog input channels and ADDR registers is shown in table 16 3 ADDR can always be read by the CPU The upper byte can be read directly but for the lower byte data transfer is performed via a temporary register TEMP For details see section 16 3 Int...

Page 624: ...lag ADF Status flag that indicates the end of A D conversion Bit 7 ADF Description 0 Clearing conditions Initial value When 0 is written to the ADF flag after reading ADF 1 When the DTC is activated by an ADI interrupt and ADDR is read 1 Setting conditions Single mode When A D conversion ends Scan mode When A D conversion ends on all specified channels Bit 6 A D Interrupt Enable ADIE Selects enabl...

Page 625: ...s until ADST is cleared to 0 by software a reset or a transition to standby mode or module stop mode Bit 4 Scan Mode SCAN Selects single mode or scan mode as the A D conversion operating mode See section 16 4 Operation for single mode and scan mode operation Only set the SCAN bit while conversion is stopped ADST 0 Bit 4 SCAN Description 0 Single mode Initial value 1 Scan mode Bit 3 Channel Select ...

Page 626: ... channel while conversion is stopped ADST 0 Channel Selection Description CH3 CH2 CH1 CH0 Single Mode SCAN 0 Scan Mode SCAN 1 0 0 0 0 AN0 Initial value AN0 1 AN1 AN0 AN1 1 0 AN2 AN0 to AN2 1 AN3 AN0 to AN3 1 0 0 AN4 AN4 1 AN5 AN4 AN5 1 0 AN6 AN4 to AN6 1 AN7 AN4 to AN7 1 0 0 0 AN8 AN8 1 AN9 AN8 AN9 1 0 AN10 AN8 to AN10 1 AN11 AN8 to AN11 ...

Page 627: ...ed ADST 0 Bit 7 Bit 6 TRGS1 TRGS0 Description 0 0 A D conversion start by software is enabled Initial value 1 A D conversion start by TPU conversion start trigger is enabled 1 0 Setting prohibited 1 A D conversion start by external trigger pin ADTRG is enabled Bits 5 4 1 and 0 Reserved These bits are reserved they are always read as 1 and cannot be modified Bits 3 and 2 Clock Select 1 and 0 CKS1 C...

Page 628: ...converter operation stops at the end of the bus cycle and a transition is made to module stop mode Registers cannot be read or written to in module stop mode For details see section 22 5 Module Stop Mode MSTPCRA is initialized to H 3F by a reset and in hardware standby mode It is not initialized by a reset and in software standby mode Bit 1 Module Stop MSTPA1 Specifies the A D converter module sto...

Page 629: ...yte value is transferred to TEMP Next when the lower byte is read the TEMP contents are transferred to the CPU When reading ADDR always read the upper byte before the lower byte It is possible to read only the upper byte but if only the lower byte is read incorrect data may be obtained Figure 16 2 shows the data flow for ADDR access Bus master H AA ADDRnH H AA ADDRnL H 40 Lower byte read ADDRnH H ...

Page 630: ...t A D conversion After making the necessary changes set the ADST bit to 1 to start A D conversion again The ADST bit can be set at the same time as the operating mode or input channel is changed Typical operations when channel 1 AN1 is selected in single mode are described next Figure 16 3 shows a timing diagram for this example 1 Single mode is selected SCAN 0 input channel AN1 is selected CH3 0 ...

Page 631: ...ate of channel 3 AN3 Note Vertical arrows indicate instructions executed by software Set Set Clear Clear A D conversion result 1 A D conversion A D conversion result 2 Read conversion result Read conversion result Idle Idle Idle Idle Idle Idle A D conversion Set Figure 16 3 Example of A D Converter Operation Single Mode Channel 1 Selected ...

Page 632: ... be set at the same time as the operating mode or input channel is changed Typical operations when three channels AN0 to AN2 are selected in scan mode are described next Figure 16 4 shows a timing diagram for this example 1 Scan mode is selected SCAN 1 channel set 0 is selected CH3 0 scan group 0 is selected CH2 0 analog input channels AN0 to AN2 are selected CH1 1 CH0 0 and A D conversion is star...

Page 633: ...a currently being converted is ignored Clear 1 Idle Idle A D conversion time Idle Continuous A D conversion execution A D conversion 1 Idle Idle Idle Idle Idle Transfer 2 A D conversion 3 A D conversion 2 A D conversion 4 A D conversion result 1 A D conversion result 2 A D conversion result 3 A D conversion result 4 A D conversion 5 Figure 16 4 Example of A D Converter Operation Scan Mode 3 Channe...

Page 634: ... varies depending on the timing of the write access to ADCSR The total conversion time therefore varies within the ranges indicated in table 16 4 In scan mode the values given in table 16 4 apply to the first conversion time The values given in table 16 5 apply to the second and subsequent conversions In both cases set bits CKS1 and CKS0 in ADCR to give a conversion time of at least 10 µs 1 2 tD t...

Page 635: ...CKS1 CKS0 Conversion Time State 0 0 512 Fixed 1 256 Fixed 1 0 128 Fixed 1 64 Fixed 16 4 4 External Trigger Input Timing A D conversion can be externally triggered When the TRGS1 and TRGS0 bits are set to 11 in ADCR external trigger input is enabled at the ADTRG pin A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR starting A D conversion Other operations in both single and scan modes...

Page 636: ...nalog input voltage range The voltage applied to analog input pin ANn during A D conversion should be in the range AVSS ANn Vref 2 Relation between AVCC AVSS and VCC VSS As the relationship between AVSS and VSS set AVSS VSS If the A D converter is not used set AVCC VCC and do not leave the AVCC and AVSS pins open or no account 3 Vref input range The analog reference voltage input at the Vref pin s...

Page 637: ...ected to AVCC and Vref and the filter capacitor connected to AN0 to AN11 must be connected to AVSS If a filter capacitor is connected as shown in figure 16 7 the input currents at the analog input pins AN0 to AN11 are averaged and so an error may arise Also when A D conversion is performed frequently as in scan mode if the current charged and discharged by the capacitance of the sample and hold ci...

Page 638: ... the minimum voltage value B 0000000000 H 00 to B 0000000001 H 01 see figure 16 10 Full scale error The deviation of the analog input voltage value from the ideal A D conversion characteristic when the digital output changes from B 1111111110 H 3E to B 1111111111 H 3F see figure 16 10 Quantization error The deviation inherent in the A D converter given by 1 2 LSB see figure 16 9 Nonlinearity error...

Page 639: ...1 110 101 100 011 010 001 000 FS Quantization error Digital output Ideal A D conversion characteristic Analog input voltage 1 1024 2 1024 1022 1024 1023 1024 Figure 16 9 A D Conversion Precision Definitions 1 ...

Page 640: ...er s sample and hold circuit input capacitance to be charged within the sampling time if the sensor output impedance exceeds 10 kΩ charging may be insufficient and it may not be possible to guarantee the A D conversion precision However if a large capacitance is provided externally the input load will essentially comprise only the internal input resistance of 10 kΩ and the signal source impedance ...

Page 641: ...nection to an electrically stable GND such as AVSS Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board so acting as antennas A D converter equivalent circuit H8S 2646 Series 20 pF Cin 15 pF 10 kΩ to 5 kΩ Low pass filter C to 0 1 µF Sensor output impedance Sensor input Figure 16 11 Example of Analog Input Circuit ...

Page 642: ...610 ...

Page 643: ...ers PWBFR with data transferred automatically every cycle Channel 1 has four duty registers and four buffer registers Channel 2 has eight duty registers and four buffer registers 0 to 100 duty A duty cycle of 0 to 100 can be set by means of a duty register setting Five operating clocks There is a choice of five operating clocks ø ø 2 ø 4 ø 8 ø 16 On chip output driver High speed access via interna...

Page 644: ... PWM1D PWBFR1C PWDTR1E P N P N PWM1E PWM1F PWBFR1E PWDTR1G P N P N PWM1G PWM1H PWBFR1G PWCR1 PWOCR1 Compare match Interrupt request Internal data bus Bus interface Port control Legend PWCR1 PWM control register 1 PWOCR1 PWM output control register 1 PWPR1 PWM polarity register 1 PWCNT1 PWM counter 1 PWCYR1 PWM cycle register 1 PWDTR1A 1C 1E 1G PWM duty registers 1A 1C 1E 1G PWBFR1A 1C 1E 1G PWM bu...

Page 645: ...WM2B PWM2C PWM2D PWM2E PWM2F PWM2G PWM2H 9 0 Compare match ø ø 2 ø 4 ø 8 ø 16 Legend PWCR2 PWM control register 2 PWOCR2 PWM output control register 2 PWPR2 PWM polarity register 2 PWCNT2 PWM counter 2 PWCYR2 PWM cycle register 2 PWDTR2A to PWDTR2H PWM duty registers 2A to 2H PWBFR2A 2B 2C 2D PWM buffer registers 2A 2B 2C 2D Internal data bus Interrupt request Bus interface Port control Figure 17 ...

Page 646: ...output PWM output pin 1F PWM1F Output Channel 1F PWM output PWM output pin 1G PWM1G Output Channel 1G PWM output PWM output pin 1H PWM1H Output Channel 1H PWM output PWM output pin 2A PWM2A Output Channel 2A PWM output PWM output pin 2B PWM2B Output Channel 2B PWM output PWM output pin 2C PWM2C Output Channel 2C PWM output PWM output pin 2D PWM2D Output Channel 2D PWM output PWM output pin 2E PWM2...

Page 647: ...egister 1C PWBFR1C R W H EC00 H FC0A PWM buffer register 1E PWBFR1E R W H EC00 H FC0C PWM buffer register 1G PWBFR1G R W H EC00 H FC0E 2 PWM control register 2 PWCR2 R W H C0 H FC10 PWM output control register 2 PWOCR2 R W H 00 H FC12 PWM polarity register 2 PWPR2 R W H 00 H FC14 PWM cycle register 2 PWCYR2 R W H FFFF H FC16 PWM buffer register 2A PWBFR2A R W H EC00 H FC18 PWM buffer register 2B P...

Page 648: ...atch mode subactive mode subsleep mode and module stop mode Bits 7 and 6 Reserved Bits 7 and 6 are reserved they are always read as 1 and cannot be modified Bit 5 Interrupt Enable IE Bit 5 selects enabling or disabling of an interrupt in the event of a compare match with the PWCYR register for the corresponding channel Bit 5 IE Description 0 Interrupt disabled Initial value 1 Interrupt enabled Bit...

Page 649: ... counts on ø 8 1 Internal clock counts on ø 16 Don t care 17 2 2 PWM Output Control Registers 1 and 2 PWOCR1 PWOCR2 PWOCR1 Bit 7 6 5 4 3 2 1 0 OE1H OE1G OE1F OE1E OE1D OE1C OE1B OE1A Initial value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W PWOCR2 Bit 7 6 5 4 3 2 1 0 OE2H OE2G OE2F OE2E OE2D OE2C OE2B OE2A Initial value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W PWOC...

Page 650: ...6 5 4 3 2 1 0 OPS2H OPS2G OPS2F OPS2E OPS2D OPS2C OPS2B OPS2A Initial value 0 0 0 0 0 0 0 0 Read Write R W R W R W R W R W R W R W R W PWPR is an 8 bit read write register that selects the PWM output polarity PWPR1 controls outputs PWM1H to PWM1A and PWPR2 controls outputs PWM2H to PWM2A PWPR is initialized to H 00 upon reset and in standby mode watch mode subactive mode subsleep mode and module s...

Page 651: ...2 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read Write R W R W R W R W R W R W R W R W R W R W PWCYR is a 16 bit read write register that sets the PWM conversion cycle When a PWCYR compare match occurs PWCNT is cleared and data is transferred from the buffer register PWBFR to the duty register PWDTR PWCYR1 is used for the channel 1 conversion cycle set...

Page 652: ...t Terminal Select OTS Bit 12 selects the pin used for PWM output according to the value in bit 12 in the buffer register that is transferred by a PWCYR1 compare match Unselected pins output a low level or a high level when the corresponding bit in PWPR1 is set to 1 Register Bit 12 OTS Description PWDTR1A 0 PWM1A output selected Initial value 1 PWM1B output selected PWDTR1C 0 PWM1C output selected ...

Page 653: ...its PWM output on selected pin PWM output on unselected pin Compare match 0 1 N M M 2 M 1 M N 1 0 Figure 17 4 Duty Register Compare Match OPS 0 in PWPR1 0 1 N 1 0 N M N 2 PWCNT1 lower 10 bits PWCYR1 lower 10 bits PWDTR1 lower 10 bits PWM output M 0 PWM output 0 M N PWM output N M Figure 17 5 Differences in PWM Output According to Duty Register Set Value OPS 0 in PWPR1 ...

Page 654: ...TR1 Bits 11 and 10 Reserved These bits are always read as 1 and cannot be modified Bits 9 to 0 Duty DT Bits 9 to 0 comprise the data transferred to bits 9 to 0 in PWDTR1 17 2 8 PWM Duty Registers 2A to 2H PWDTR2A to PWDTR2H Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 Initial value 1 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 Read Write There are eight PWDTR2 registers PWDT...

Page 655: ...ompare match until a PWDTR2 compare match occurs When all the bits are 0 there is no high level output period no low level output period when the corresponding bit in PWPR2 is set to 1 PWCNT2 lower 10 bits PWCYR2 lower 10 bits PWDTR2 lower 10 bits PWM output Compare match 0 1 N M M 2 M 1 M N 1 0 Figure 17 6 Duty Register Compare Match OPS 0 in PWPR2 0 1 N 1 0 N M N 2 PWCNT2 lower 10 bits PWCYR2 lo...

Page 656: ...ue of the TDS bit PWBFR2 is initialized to H EC00 upon reset and in standby mode watch mode subactive mode subsleep mode and module stop mode Bits 15 to 13 Reserved These bits are always read as 1 and cannot be modified Bit 12 Transfer Destination Select TDS Bit 12 selects the PWDTR2 register to which data is to be transferred Register Bit 12 TDS Description PWBFR2A 0 PWDTR2A selected Initial valu...

Page 657: ...n the MSTPD7 bit is set to 1 PWM timer operation is stopped at the end of the bus cycle and module stop mode is entered For details see section 22 5 Module Stop Mode MSTPCRD is initialized by a reset and in hardware standby mode It is not initialized by a manual reset or in software standby mode Bit 7 Module Stop MSTPD7 Bit 7 specifies the PWM module stop mode Bit 7 MSTPD7 Description 0 PWM module...

Page 658: ...us Bus interface Module data bus Figure 17 8 16 Bit Register Access Operation Bus Master PWCYR1 16 Bits 17 3 2 8 Bit Data Registers PWCR1 2 PWOCR1 2 and PWPR1 2 are 8 bit registers that can be read and written to in 8 bit units These registers are linked to the bus master by a 16 bit data bus and can be read or written by 16 bit access in this case the lower 8 bits will always be read as H FF H L ...

Page 659: ... PWCR1 has been set an interrupt can be requested or the DTC can be activated Waveform Output The PWM outputs selected by the OTS bits in PWDTR1A C E G go high when a compare match occurs between PWCNT1 and PWCYR1 The PWM outputs not selected by the OTS bits are low When a compare match occurs between PWCNT1 and PWDTR1A C E G the corresponding PWM output goes low If the corresponding bit in PWPR1 ...

Page 660: ...TR2C or PWDTR2G and from PWBFR2D to PWDTR2D or PWDTR2H according to the value of the TDS bit PWCNT2 starts counting up At the same time the CMF bit in PWCR2 is set so that if the IE bit in PWCR2 has been set an interrupt can be requested or the DTC can be activated Waveform Output The PWM outputs go high when a compare match occurs between PWCNT2 and PWCYR2 When a compare match occurs between PWCN...

Page 661: ...changed in the overwrite of the duty register due to contention This may result in unanticipated duty output In the case of channel 2 the duty register used as the transfer destination is selected by the TDS bit of the buffer register when an overwrite of the duty register occurs due to contention This can also result in an unintended overwrite of the duty register Buffer register rewriting must b...

Page 662: ...630 ...

Page 663: ... SEG 1 4 24 SEG 40 SEG LCD RAM capacity 8 bits 20 bytes 160 bits Byte or word access to LCD RAM The segment output pins can be used as ports in groups of four Common output pins not used because of the duty cycle can be used for common double buffering parallel connection With 1 2 duty parallel connection of COM1 to COM2 and of COM3 to COM4 can be used In static mode parallel connection of COM1 to...

Page 664: ...RAM 20 bytes Internal data bus 24 bit shift register 1 40 bit shift register 2 LCD drive power supply Segment driver Common data latch Common driver M V1 V2 V3 VSS COM1 COM4 SEG24 SEG23 SEG22 SEG21 SEG20 SEG1 Legend LPCR LCD port control register LCR LCD control register LCR2 LCD control register 2 Notes 1 In the H8S 2646 H8S 2646R and H8S 2645 2 In the H8S 2648 H8S 2648R and H8S 2647 LPVCC H8S 26...

Page 665: ...in parallel with static or 1 2 duty LCD power supply pins V1 V2 V3 Used when a bypass capacitor is connected externally and when an external power supply circuit is used 18 1 4 Register Configuration Table 18 2 shows the register configuration of the LCD controller driver Table 18 2 LCD Controller Driver Registers Name Abbreviation R W Initial Value Address 1 LCD port control register LPCR R W H 0...

Page 666: ...ultiple pins to increase the common drive power when not all common pins are used because of the duty setting Bit 7 DTS1 Bit 6 DTS0 Bit 5 CMX Duty Cycle Common Drivers Notes 0 0 0 Static COM1 COM4 COM3 and COM2 can be used as ports Initial value 1 COM4 to COM1 COM4 COM3 and COM2 output the same waveform as COM1 1 0 1 2 duty COM2 to COM1 COM4 and COM3 can be used as ports 1 COM4 to COM1 COM4 output...

Page 667: ...xternal expansion enabled 1 SEG Port Port Port Port External expansion not possible 1 0 SEG SEG Port Port Port 1 SEG SEG SEG Port Port 1 0 0 SEG SEG SEG SEG Port 1 SEG SEG SEG SEG SEG 1 Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited 1 Setting prohibited Setting prohibited Setting prohibited Setting prohibited Setting prohibited Don t care Note When u...

Page 668: ... Port Port Port Port Port External expansion not possible 1 0 SEG SEG Port Port Port Port Port Port Port 1 SEG SEG SEG Port Port Port Port Port Port 1 0 0 SEG SEG SEG SEG Port Port Port Port Port 1 SEG SEG SEG SEG SEG Port Port Port Port 1 0 SEG SEG SEG SEG SEG SEG Port Port Port 1 SEG SEG SEG SEG SEG SEG SEG Port Port 1 0 SEG SEG SEG SEG SEG SEG SEG SEG Port 1 SEG SEG SEG SEG SEG SEG SEG SEG SEG ...

Page 669: ...andby mode the LCD power supply split resistance is disconnected from VCC regardless of the setting of this bit Bit 6 PSW Description 0 LCD power supply split resistance is disconnected from VCC Initial value 1 LCD power supply split resistance is connected to VCC Bit 5 Display Function Activate ACT Bit 5 specifies whether or not the LCD controller driver is used Clearing this bit to 0 halts opera...

Page 670: ...equired in these modes øSUB øSUB 2 or øSUB 4 must be selected as the operating clock Bit 3 Bit 2 Bit 1 Bit 0 Frame Frequency 1 CKS3 CKS2 CKS1 CKS0 Operating Clock ø 20 MHz 0 0 0 øSUB 128 Hz 2 Initial value 1 øSUB 2 64 Hz 2 1 øSUB 4 32 Hz 2 1 0 0 0 ø 8 4880 Hz 1 ø 16 2440 Hz 1 0 ø 32 1220 Hz 1 ø 64 610 Hz 1 0 0 ø 128 305 Hz 1 ø 256 152 6 Hz 1 0 ø 512 76 3 Hz 1 ø 1024 38 1 Hz Don t care Notes 1 When...

Page 671: ... to H 70 upon reset and in standby mode Bit 7 A Waveform B Waveform Switching Control LCDAB Bit 7 specifies whether the A waveform or B waveform is used as the LCD drive waveform Bit 7 LCDAB Description 0 Drive using A waveform Initial value 1 Drive using B waveform Bits 6 and 5 Reserved These bits are always read as 1 and cannot be modified Bits 4 to 0 Reserved These bits are always read as 0 and...

Page 672: ...o 1 LCD controller driver operation is stopped at the end of the bus cycle and module stop mode is entered For details see section 22 5 Module Stop Mode MSTPCRD is initialized to H FF by a reset and in hardware standby mode It is not initialized software standby mode Bit 6 Module Stop MSTPD6 Bit 6 specifies the LCD controller driver module stop mode Bit 6 MSTPD6 Description 0 LCD controller driver...

Page 673: ...fer to section 18 3 4 Boosting the LCD Drive Power Supply When static or 1 2 duty is selected the common output drive capability can be increased Set CMX to 1 when selecting the duty cycle In this mode with a static duty cycle pins COM4 to COM1 output the same waveform and with 1 2 duty the COM1 waveform is output from pins COM2 and COM1 and the COM2 waveform is output from pins COM4 and COM3 LCD ...

Page 674: ...y setting bits CKS3 to CKS0 The frame frequency should be selected in accordance with the LCD panel specification For the clock selection method in watch mode subactive mode and subsleep mode see section 18 3 3 Operation in Power Down Modes A or B waveform selection Either the A or B waveform can be selected as the LCD waveform to be used by means of LCDAB LCD drive power supply selection When an ...

Page 675: ...ay data is written to the part corresponding to the duty using the same kind of instruction as for ordinary RAM and display is started automatically when turned on Word or byte access instructions can be used for RAM setting Bit 7 H FC40 H FC47 COM4 Bit 6 COM3 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SEG2 H FC48 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 SEG1 SEG24 SEG24 SEG24 SEG24 SEG23 SEG23 SEG23 SEG23 H FC53 C...

Page 676: ...lay space Space not used for display Figure 18 4 LCD RAM Map 1 3 Duty Bit 7 SEG24 H FC40 H FC49 COM2 Bit 6 SEG24 COM1 Bit 5 SEG23 Bit 4 SEG23 Bit 3 SEG22 Bit 2 SEG22 Bit 1 SEG21 Bit 0 SEG21 SEG4 H FC44 H FC43 SEG4 SEG3 SEG3 SEG2 SEG2 SEG1 SEG1 H FC53 COM2 COM1 COM2 COM1 COM2 COM1 Space not used for display Space not used for display Display space Figure 18 5 LCD RAM Map 1 2 Duty ...

Page 677: ...t 0 H FC40 H FC41 SEG8 H FC42 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG24 H FC44 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 H FC53 COM1 COM1 COM1 COM1 COM1 COM1 Space not used for display Space not used for display Display space Figure 18 6 LCD RAM Map Static Mode ...

Page 678: ...isplay data is written to the part corresponding to the duty using the same kind of instruction as for ordinary RAM and display is started automatically when turned on Word or byte access instructions can be used for RAM setting Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H FC40 H FC53 SEG40 SEG40 SEG40 SEG39 SEG40 SEG39 SEG39 SEG39 SEG2 SEG2 SEG2 SEG1 SEG2 SEG1 SEG1 SEG1 COM3 COM2 COM1 COM3 C...

Page 679: ...t used for display COM2 COM1 COM3 COM2 COM1 Figure 18 8 LCD RAM Map 1 3 Duty Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H FC40 H FC53 COM2 COM1 COM2 COM1 COM2 COM1 COM2 COM1 SEG40 SEG40 SEG39 SEG39 SEG38 SEG38 SEG37 SEG37 SEG4 SEG4 SEG3 SEG3 SEG2 SEG2 SEG1 SEG1 H FC49 Display space Space not used for display Figure 18 9 LCD RAM Map 1 2 Duty ...

Page 680: ...2 Bit 1 Bit 0 H FC40 H FC53 COM1 COM1 COM1 COM1 COM1 COM1 COM1 COM1 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 H FC44 Display space Space not used for display Figure 18 10 LCD RAM Map Static Mode ...

Page 681: ... V1 V2 V3 VSS V1 V2 V3 VSS a Waveform with 1 4 duty 1 frame M Data COM1 COM2 COM3 SEGn 1 frame M Data COM1 COM2 SEGn V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS 1 frame M Data COM1 SEGn V1 VSS V1 VSS b Waveform with 1 3 duty c Waveform with 1 2 duty d Waveform with static output Figure 18 11 Output Waveforms for Each Duty Cycle A Waveform ...

Page 682: ...SS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS COM2 a Waveform with 1 4 duty M Data COM1 COM2 COM3 COM4 SEGn 1 frame 1 frame 1 frame 1 frame V1 V2 V3 VSS V1 V2 V3 VSS V1 V2 V3 VSS 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame Figure 18 12 Output Waveforms for Each Duty Cycle B Waveform ...

Page 683: ...mode the system clock oscillator stops and therefore unless øSUB øSUB 2 or øSUB 4 has been selected by bits CKS3 to CKS0 the clock will not be supplied and display will halt Since there is a possibility that a direct current will be applied to the LCD panel in this case it is essential to ensure that øSUB øSUB 2 or øSUB 4 is selected In active medium speed mode the system clock is switched and the...

Page 684: ...2 The LCD drive power supply is turned off regardless of the setting of the PSW bit 3 Display operation is performed only if øSUB øSUB 2 or øSUB 4 is selected as the operating clock 4 The clock supplied to the LCD stops 18 3 4 Boosting the LCD Drive Power Supply When a panel is driven the on chip power supply capacity may be insufficient The recommended solution in this case is to connect bypass c...

Page 685: ...possible to perform fast word data transfer The on chip RAM can be enabled or disabled by means of the RAM enable bit RAME in the system control register SYSCR 19 1 1 Block Diagram Figure 19 1 shows a block diagram of the on chip RAM Internal data bus upper 8 bits Internal data bus lower 8 bits H FFE000 H FFE002 H FFE004 H FFFFC0 H FFE001 H FFE003 H FFE005 H FFFFC1 H FFFFFE H FFFFFF H FFEFBE H FFE...

Page 686: ...ol Register SYSCR 7 MACS 0 R W 6 0 5 INTM1 0 R W 4 INTM0 0 R W 3 NMIEG 0 R W 0 RAME 1 R W 2 0 R W 1 0 Bit Initial value R W The on chip RAM is enabled or disabled by the RAME bit in SYSCR For details of other bits in SYSCR see section 3 2 2 System Control Register SYSCR Bit 0 RAM Enable RAME Enables or disables the on chip RAM The RAME bit is initialized when the reset state is released It is not ...

Page 687: ...n to and read in byte or word units Each type of access can be performed in one state Even addresses use the upper 8 bits and odd addresses use the lower 8 bits Word data must start at an even address 19 4 Usage Notes When Using the DTC DTC register information can be located in addresses H FFEBC0 to H FFEFBF When the DTC is used the RAME bit must not be cleared to 0 Reserved Areas Addresses H FFB...

Page 688: ...656 ...

Page 689: ...o 78 µs typ per byte and the erase time is 100 ms typ Reprogramming capability The flash memory can be reprogrammed up to 100 times On board programming modes There are two modes in which flash memory can be programmed erased verified on board Boot mode User program mode Automatic bit rate adjustment With data transfer in boot mode the LSI s bit rate can be automatically adjusted to match the tran...

Page 690: ...ess bus Internal data bus 16 bits FWE pin Mode pin EBR1 EBR2 RAMER FLPWCR FLMCR1 Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Flash memory power control register Legend FLMCR1 FLMCR2 EBR1 EBR2 RAMER FLPWCR Figure 20 1 Block Diagram of Flash Memory ...

Page 691: ...es are provided as modes to write and erase the flash memory Boot mode On board programming mode User program mode User mode on chip ROM enabled Reset state Programmer mode RES 0 FWE 1 FWE 0 1 1 2 Notes Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory 1 RAM emulation possible 2 MD0 0 MD1 0 MD2 0 P14 0 FWE 1 P16 0 PF0 1 RES 0 MD1 1 MD2 0 ...

Page 692: ...the host 2 Programming control program transfer When boot mode is entered the boot program in the LSI originally incorporated in the chip is started and the programming control program in the host is transferred to RAM via SCI communication The boot program required for flash memory erasing is automatically transferred to the RAM boot program area 3 Flash memory initialization The erase program in...

Page 693: ...erase control program should be prepared in the host or in the flash memory 2 Programming erase control program transfer When user program mode is entered user software confirms this fact executes transfer program in the flash memory and transfers the programming erase control program to RAM 3 Flash memory initialization The programming erase program in RAM is executed and the flash memory is init...

Page 694: ...ory Emulation block RAM SCI Overlap RAM emulation is performed on data written in RAM Figure 20 3 Reading Overlap RAM Data in User Mode or User Program Mode When overlap RAM data is confirmed the RAMS bit is cleared RAM overlap is released and writes should actually be performed to the flash memory When the programming control program is transferred to RAM ensure that the transfer destination and ...

Page 695: ... 4 Writing Overlap RAM Data in User Program Mode 20 2 5 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Total erase Yes Yes Block erase No Yes Programming control program 2 1 2 3 1 Erase erase verify 2 Program program verify 3 Emulation Note To be provided by the user in accordance with the recommended algorithm ...

Page 696: ...ded into two 32 kbytes blocks one 28 kbytes block one 16 kbytes block two 8 kbytes blocks and four 1 kbyte blocks Address H 00000 Address H 1FFFF 128 kbytes 28 kbytes 32 kbytes 32 kbytes 16 kbytes 8 kbytes 8 kbytes 1 kbyte 4 Figure 20 5 Block Configuration ...

Page 697: ...e protection by hardware Mode 2 MD2 Input Sets LSI operating mode Mode 1 MD1 Input Sets LSI operating mode Mode 0 MD0 Input Sets LSI operating mode Port F0 PF0 Input Sets LSI operating mode when MD2 MD1 MD0 0 Port 16 P16 Input Sets LSI operating mode when MD2 MD1 MD0 0 Port 14 P14 Input Sets LSI operating mode when MD2 MD1 MD0 0 Transmit data TxD1 Output Serial transmit data output Receive data Rx...

Page 698: ...ers 20 5 Register Descriptions 20 5 1 Flash Memory Control Register 1 FLMCR1 FLMCR1 is an 8 bit register used for flash memory operating mode control Program verify mode or erase verify mode for addresses H 00000 to H 1FFFF is entered by setting SWE bit to 1 when FWE 1 then setting the PV or EV bit Program mode for addresses H 00000 to H 1FFFF is entered by setting SWE bit to 1 when FWE 1 then set...

Page 699: ...the FWE pin Bit 6 Software Write Enable Bit SWE Enables or disables flash memory programming and erasing Set this bit when setting bits 5 to 0 bits 7 to 0 of EBR1 and bits 1 and 0 of EBR2 Bit 6 SWE Description 0 Writes disabled Initial value 1 Writes enabled Setting condition When FWE 1 Bit 5 Erase Setup Bit ESU Prepares for a transition to erase mode Set this bit to 1 before setting the E bit in ...

Page 700: ... Description 0 Erase verify mode cleared Initial value 1 Transition to erase verify mode Setting condition When FWE 1 and SWE 1 Bit 2 Program Verify PV Selects program verify mode transition or clearing Do not set the SWE ESU PSU EV E or P bit at the same time Bit 2 PV Description 0 Program verify mode cleared Initial value 1 Transition to program verify mode Setting condition When FWE 1 and SWE 1...

Page 701: ...3 2 1 0 FLER Initial value 0 0 0 0 0 0 0 0 R W R R R R R R R R Note FLMCR2 is a read only register and should not be written to Bit 7 Flash Memory Error FLER Indicates that an error has occurred during an operation on flash memory programming or erasing When FLER is set to 1 flash memory goes to the error protection state Bit 7 FLER Description 0 Flash memory is operating normally Initial value Fl...

Page 702: ...EB1 EB0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W 20 5 4 Erase Block Register 2 EBR2 EBR2 is an 8 bit register that specifies the flash memory erase area block by block EBR2 is initialized to H 00 by a reset in hardware standby mode and software standby mode when a low level is input to the FWE pin Bit 0 will be initialized to 0 if bit SWE of FLMCR1 is not set even though a...

Page 703: ... memory programming RAMER initialized to H 00 by a reset and in hardware standby mode It is not initialized by software standby mode RAMER settings should be made in user mode or user program mode Flash memory area divisions are shown in table 20 4 To ensure correct operation of the emulation function the ROM for which RAM emulation is performed should not be accessed immediately after this regist...

Page 704: ... See table 20 4 Table 20 4 Flash Memory Area Divisions Addresses Block Name RAMS RAM2 RAM1 RAM0 H FFE000 H FFE3FF RAM area 1 kB 0 H 000000 H 0003FF EB0 1 kB 1 0 0 H 000400 H 0007FF EB1 1 kB 1 0 1 H 000800 H 000BFF EB2 1 kB 1 1 0 H 000C00 H 000FFF EB3 1 kB 1 1 1 Don t care 20 5 6 Flash Memory Power Control Register FLPWCR Bit 7 6 5 4 3 2 1 0 PDWND Initial value 0 0 0 0 0 0 0 0 R W R W R R R R R R R...

Page 705: ... mode 1 1 1 0 Single chip mode 1 1 1 20 6 1 Boot Mode When boot mode is used the flash memory programming control program must be prepared in the host beforehand The SCI channel to be used is set to asynchronous mode When a reset start is executed after the LSI s pins have been set to boot mode the boot program built into the LSI is started and the programming control program prepared in the host ...

Page 706: ...674 RxD1 TxD1 SCI1 LSI Flash memory Write data reception Verify data transmission Host On chip RAM Figure 20 6 System Configuration in Boot Mode ...

Page 707: ...mits one H 55 data byte After receiving H 55 LSI transmits one H AA data byte to host Host transmits number of programming control program bytes N upper byte followed by lower byte LSI transmits received number of bytes to host as verify data echo back n 1 Host transmits programming control program sequentially in byte units LSI transmits received programming control program to host as verify data...

Page 708: ...ormed normally initiate boot mode again reset and repeat the above operations Depending on the host s transmission bit rate and the LSI s system clock frequency there will be a discrepancy between the bit rates of the host and the LSI Set the host transfer bit rate at 19 200 9 600 or 4 800 bps to operate the SCI properly Table 20 6 shows host transfer bit rates and system clock frequencies for whi...

Page 709: ...t of reset in boot mode it measures the low level period of the input at the SCI s RxD1 pin The reset should end with RxD1 high After the reset ends it takes approximately 100 states before the chip is ready to measure the low level period of the RxD1 pin In boot mode if any data has been programmed into the flash memory if all data is not 1 all flash memory blocks are erased Boot mode is for use ...

Page 710: ... prevent these pins from becoming output signal pins during a reset or to prevent collision with signals outside the microcomputer Notes 1 Mode pin and FWE pin input must satisfy the mode programming setup time tMDS 4 states with respect to the reset release timing 2 For more information on FWE application cancel refer to section 20 13 Flash Memory Programming and Erasing Precautions 3 See Appendi...

Page 711: ...the FWE assessment program and transfer program and the program erase control program if necessary beforehand Note Do not apply a constant high level to the FWE pin Apply a high level to the FWE pin only when the flash memory is programmed or erased Also while a high level is applied to the FWE pin the watchdog timer should be activated to prevent overprogramming or overerasing due to program runa...

Page 712: ...rogram is in external memory an instruction for writing to flash memory and the following instruction must be in the on chip RAM The DTC must not be activated before or after execution of an instruction for writing to flash memory In the following operation descriptions wait times after setting or clearing individual bits in FLMCR1 are given as parameters for details of the wait times see section ...

Page 713: ... performed during the programming erasing process 1 Normal mode On board programming mode 2 Do not make a state transition by setting or clearing multiple bits simultaneously 3 After a transition from erase mode to the erase setup state do not enter erase mode without passing through the software programming enable state 4 After a transition from program mode to the program setup state do not ente...

Page 714: ... be H 00 and H 80 128 consecutive byte data transfers are performed The program address and program data are latched in the flash memory A 128 byte data transfer must be performed even if writing fewer than 128 bytes in this case H FF data must be written to the extra addresses Next the watchdog timer WDT is set to prevent overprogramming due to program runaway etc Set a value greater than tspsu t...

Page 715: ...f the program program verify sequence is indicated by the maximum programming count N Leave a wait time of at least tcswe µs after clearing SWE Notes on Program Program Verify Procedure 1 In order to perform 128 byte unit programming the lower 8 bits of the write start address must be H 00 or H 80 2 When performing continuous writing of 128 byte data to flash memory byte unit transfer should be us...

Page 716: ...o that bit 5 The period for which the P bit in FLMCR1 is set the write pulse width should be changed according to the degree of progress through the program program verify procedure For detailed wait time specifications see section 23 7 Flash Memory Characteristics Item Symbol Item Symbol Wait time after tsp When reprogramming loop count n is 1 to 6 tsp30 P bit setting When reprogramming loop coun...

Page 717: ...executed 0 1 1 Programming by write pulse application incomplete additional programming processing not to be executed 1 0 1 Programming already completed additional programming processing not to be executed 1 1 1 Still in erased state no action Legend Y Data of bits on which additional programming is executed X Data of bits on which reprogramming is executed in a certain reprogramming loop 7 It is...

Page 718: ...from additional programming data area in RAM to flash memory Reprogram Data Computation Table Reprogram Data X Verify Data V Additional Programming Data Y 1 1 1 1 0 1 0 0 0 0 1 1 Comments Additional programming to be executed Additional programming not to be executed Additional programming not to be executed Additional programming not to be executed 0 1 1 1 0 1 0 1 0 0 1 1 Additional Programming D...

Page 719: ...d after memory has been erased to check whether it has been correctly erased After the elapse of the fixed erase time clear the E bit in FLMCR1 then wait for at least tce µs before clearing the ESU bit to exit erase mode After exiting erase mode the watchdog timer setting is also cleared The operating mode is then switched to erase verify mode by setting the EV bit in FLMCR1 Before reading in eras...

Page 720: ...LMCR1 Disable WDT Erase halted 1 Verify data all 1s Last address of block Erase failure Clear SWE bit in FLMCR1 n N No No No Yes Yes Yes n n 1 Increment address Wait tcswe µs Wait tcswe µs Notes 1 Prewriting setting erase block data to all 0s is not necessary 2 Verify data is read in 16 bit word units 3 Make only a single bit specification in the erase block registers EBR1 and EBR2 Two or more bit...

Page 721: ... error protected state See table 20 7 Table 20 7 Hardware Protection Functions Item Description Program Erase FWE pin protection When a low level is input to the FWE pin FLMCR1 FLMCR2 except bit FLER EBR1 and EBR2 are initialized and the program erase protected state is entered Yes Yes Reset standby protection In a reset including a WDT reset and in standby mode FLMCR1 FLMCR2 EBR1 and EBR2 are ini...

Page 722: ...tion Functions Item Description Program Erase SWE bit protection Setting bit SWE in FLMCR1 to 0 will place area H 000000 to H 01FFFF in the program erase protected state Execute the program in the on chip RAM external memory Yes Yes Block specification protection Erase protection can be set for individual blocks by settings in erase block register 1 EBR1 and erase block register 2 EBR2 Setting EBR...

Page 723: ...BR2 settings are retained but program mode or erase mode is aborted at the point at which the error occurred Program mode or erase mode cannot be re entered by re setting the P or E bit However PV and EV bit setting is enabled and a transition can be made to verify mode FLER bit setting conditions are as follows 1 When the flash memory of the relevant address area is read during programming erasin...

Page 724: ...ction mode software standby Software standby mode FLMCR1 FLMCR2 except bit FLER EBR1 EBR2 initialization state FLMCR1 FLMCR2 EBR1 EBR2 initialization state Software standby mode release RD Memory read possible VF Verify read possible PR Programming possible ER Erasing possible RD Memory read not possible VF Verify read not possible PR Programming not possible ER Erasing not possible Legend RES 0 o...

Page 725: ...esses cannot be made from the flash memory area or the RAM area overlapping flash memory Emulation can be performed in user mode and user program mode Figure 20 14 shows an example of emulation of real time flash memory programming Start of emulation program End of emulation program Tuning OK Yes No Set RAMER Write tuning data to overlap RAM Execute application program Clear RAMER Write to flash m...

Page 726: ...bit is cleared releasing RAM overlap 4 The data written in the overlapping RAM is written into the flash memory space EB0 Notes 1 When the RAMS bit is set to 1 program erase protection is enabled for all blocks regardless of the value of RAM2 to RAM0 emulation protection In this state setting the P or E bit in flash memory control register 1 FLMCR1 will not cause a transition to program mode or er...

Page 727: ...rasing flash memory NMI interrupt is also disabled in the error protection state while the P or E bit remains set in FLMCR1 Notes 1 Interrupt requests must be disabled inside and outside the MCU until the programming control program has completed programming 2 The vector may not be read correctly in this case for the following two reasons If flash memory is read while being programmed or erased wh...

Page 728: ...PLLCAP PLLVSS pins Oscillator circuit VCL Internal step down circuit 20 11 1 Socket Adapter Pin Correspondence Diagram Connect the socket adapter to the chip as shown in figure 20 17 This will enable conversion to a 40 pin arrangement The on chip ROM memory map is shown in figure 20 16 and the socket adapter pin correspondence diagram in figure 20 17 H 000000 Addresses in MCU mode Addresses in pro...

Page 729: ...E VCC VSS NC A20 PE3 RES XTAL EXTAL PLLCAP PLLVSS VCL N C OPEN 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 47 48 49 50 13 14 15 16 17 18 19 20 11 9 10 97 7 83 94 96 87 86 93 Other than the above 1 21 56 66 84 85 91 92 98 119 126 127 8 12 40 51 61 71 72 73 74 88 89 95 105 107 123 144 VCC LPVcc AVcc Vref PWMVcc etc VSS AVss PWMVss etc Oscillator circuit PLL circuit Legend FWE I O0 to 7 A20 to 0 ...

Page 730: ... end of auto programming Status Read Mode Status polling is used for auto programming and auto erasing and normal termination can be confirmed by reading the I O6 signal In status read mode error information is output if an error occurs Table 20 10 Settings for Various Operating Modes in Programmer Mode Pin Names Mode FWE CE OE WE I O7 I O0 A18 A0 Read H or L L L H Data output Ain Output disable H...

Page 731: ...se status read operations a transition is made to the command wait state When reading memory contents a transition to memory read mode must first be made with a command write after which the memory contents are read 2 In memory read mode command writes can be performed in the same way as in the command wait state 3 Once memory read mode has been entered consecutive reads can be performed 4 After p...

Page 732: ... for Memory Read after Memory Write Table 20 13 AC Characteristics in Transition from Memory Read Mode to Another Mode Conditions VCC 5 0 V 0 5 V VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Command write cycle tnxtc 20 µs CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns WE rise time tr 30 ns WE fall time tf 30 ns ...

Page 733: ...o Another Mode Table 20 14 AC Characteristics in Memory Read Mode Conditions VCC 5 0 V 0 5 V VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Access time tacc 20 µs CE output delay time tce 150 ns OE output delay time toe 150 ns Output disable delay time tdf 100 ns Data output hold time toh 5 ns CE A18 A0 OE WE I O7 I O0 VIL VIL VIH tacc tacc toh toh Address stable Address stable Figure 20 20 CE and O...

Page 734: ... a memory write operation but a write error will be flagged 4 Memory address transfer is performed in the second cycle figure 20 22 Do not perform transfer after the third cycle 5 Do not perform a command write during a programming operation 6 Perform one auto program operation for a 128 byte block for each address Two or more additional programming operations cannot be performed on a previously p...

Page 735: ... Status polling access time tspa 150 ns Address setup time tas 0 ns Address hold time tah 60 ns Memory write time twrite 1 3000 ms Write setup time tpns 100 ns Write end setup time tpnh 100 ns WE rise time tr 30 ns WE fall time tf 30 ns CE A18 A0 FWE OE WE I O7 I O6 I O5 I O0 tpns twep tds tdh tf tr tas tah twsts twrite tspa tces tceh tnxtc tnxtc tpnh Address stable H 40 H 00 Data transfer 1 to 12...

Page 736: ...write As long as the next command write has not been performed reading is possible by enabling CE and OE Table 20 16 AC Characteristics in Auto Erase Mode Conditions VCC 5 0 V 0 5 V VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Command write cycle tnxtc 20 µs CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns Status polling...

Page 737: ...WE OE WE I O7 I O6 I O5 I O0 tens twep tds tdh tf tr tests terase tspa tces tceh tnxtc tnxtc tenh H 20 H 20 H 00 Erase end decision signal Erase normal end decision signal Figure 20 23 Auto Erase Mode Timing Waveforms ...

Page 738: ...0 5 V VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Read time after command write tnxtc 20 µs CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns OE output delay time toe 150 ns Disable delay time tdf 100 ns CE output delay time tce 150 ns WE rise time tr 30 ns WE fall time tf 30 ns CE A18 A0 OE WE I O7 I O0 twep tf tr toe t...

Page 739: ...ag indicates the operating status in auto program auto erase mode 2 The I O6 status polling flag indicates a normal or abnormal end in auto program auto erase mode Table 20 19 Status Polling Output Truth Table Pin Name During Internal Operation Abnormal End Normal End I O7 0 1 0 1 I O6 0 0 1 1 I O0 I O5 0 0 0 0 20 11 8 Programmer Mode Transition Time Commands cannot be accepted during the oscillat...

Page 740: ...d carry out auto erasing before auto programming 2 When performing programming using programmer mode on a chip that has been programmed erased in an on board programming mode auto erasing is recommended before carrying out auto programming Notes 1 The flash memory is initially in the erased state when the device is shipped by Hitachi For other chips for which the erasure history is unknown it is r...

Page 741: ...le 20 21 Flash Memory Operating States LSI Operating State Flash Memory Operating State High speed mode Medium speed mode Sleep mode Normal mode read write Subactive mode Subsleep mode When PDWND 0 Power down mode read only When PDWND 1 Normal mode read only Watch mode Software standby mode Hardware standby mode Standby mode 20 12 1 Notes on Power Down States 1 When the flash memory is in a power ...

Page 742: ...on and power off timing requirements should also be satisfied in the event of a power failure and subsequent recovery 3 FWE application disconnection see figures 20 26 to 20 28 FWE application should be carried out when MCU operation is in a stable condition If MCU operation is not stable fix the FWE pin low and set the protection state The following points must be observed concerning FWE applicat...

Page 743: ...lash memory only for verify operations verification during programming erasing Do not clear the SWE bit during programming erasing or verifying Similarly when using the RAM emulation function while a high level is being input to the FWE pin the SWE bit must be cleared before executing a program or reading data in flash memory However the RAM area overlapping flash memory space can be read and writ...

Page 744: ...s prohibited φ VCC FWE tOSC1 Min 0 µs tMDS 3 tMDS 3 MD2 to MD0 1 RES SWE bit SWE set SWE cleared Program ming erasing possible Wait time x Wait time 100 µs Min 0 µs Notes 1 Except when switching modes the level of the mode pins MD2 to MD0 must be fixed until power off by pulling the pins up or down 2 See section 23 7 Flash Memory Characteristics 3 Mode programming setup time tMDS min 200 ns Figure...

Page 745: ...tions prohibited φ VCC FWE tOSC1 Min 0 µs MD2 to MD0 1 RES SWE bit SWE set SWE cleared Program ming erasing possible Wait time x Wait time 100 µs tMDS 3 Notes 1 Except when switching modes the level of the mode pins MD2 to MD0 must be fixed until power off by pulling the pins up or down 2 See section 23 7 Flash Memory Characteristics 3 Mode programming setup time tMDS min 200 ns Figure 20 27 Power...

Page 746: ... time x Wait time 100 µs Wait time 100 µs Mode change 1 User mode User program mode Notes 1 When entering boot mode or making a transition from boot mode to another mode mode switching must be carried out by means of RES input The state of ports with multiplexed address functions and bus control output pins AS RD WR will change during this switchover interval the interval during which the RES pin ...

Page 747: ...performed by software by means of settings in the system clock control register SCKCR and low power control register LPWRCR 21 1 1 Block Diagram Figure 21 1 shows a block diagram of the clock pulse generator Legend LPWRCR SCKCR Low power control register System clock control register EXTAL XTAL PLL circuit 1 2 4 Medium speed clock divider System clock oscillator Clock selection circuit ø SUB WDT1 ...

Page 748: ...bit readable writable register that performs ø clock output control and medium speed mode control selection of operation when the PLL circuit frequency multiplication factor is changed and medium speed mode control SCKCR is initialized to H 00 by a reset and in hardware standby mode It is not initialized in software standby mode Bit 7 ø Clock Output Disable PSTOP Controls ø output Bit 7 Descriptio...

Page 749: ...K0 Description 0 0 0 Bus master is in high speed mode Initial value 1 Medium speed clock is ø 2 1 0 Medium speed clock is ø 4 1 Medium speed clock is ø 8 1 0 0 Medium speed clock is ø 16 1 Medium speed clock is ø 32 1 21 2 2 Low Power Control Register LPWRCR 7 DTON 0 R W 6 LSON 0 R W 5 NESEL 0 R W 4 SUBSTP 0 R W 3 RFCUT 0 R W 0 STC0 0 R W 2 0 R W 1 STC1 0 R W Bit Initial value Read Write LPWRCR is...

Page 750: ...y defined in section 23 Electrical Characteristics 21 3 Oscillator A crystal oscillator is used to supply clock pulses In either case the input clock should be from 4 MHz to 20 MHz 21 3 1 Connecting a Crystal Resonator Circuit Configuration A crystal resonator can be connected as shown in the example in figure 21 2 Select the damping resistance Rd according to table 21 2 An AT cut parallel resonan...

Page 751: ... Circuit Table 21 3 Crystal Resonator Parameters Frequency MHz 4 8 12 16 20 RS max Ω 120 80 60 50 40 C0 max pF 7 7 7 7 7 Note on Board Design When a crystal resonator is connected the following points should be noted Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation See figure 21 4 When designing the board place the ...

Page 752: ...recommended values Figure 21 5 Points for Attention when Using PLL Oscillation Circuit Place oscillation stabilization capacitor C1 and resistor R1 close to the PLLCAP pin and ensure that no other signal lines cross this line Supply the C1 ground from PLLVSS Separate PLLVSS from the other VSS lines at the board power supply source and be sure to insert bypass capacitors CB close to the pins ...

Page 753: ... watch mode or subactive mode 4 The clock pulse generator stops and the value set in STC1 and STC0 becomes valid 5 Software standby mode watch mode or subactive mode is cleared and a transition time is secured in accordance with the setting in STS2 to STS0 6 After the set transition time has elapsed the LSI resumes operation using the target multiplication factor If a PC break is set for the SLEEP...

Page 754: ...p Note C1 and C2 are reference values that include the wiring capacity Figure 21 6 Example Connection of 32 768kHz Quartz Oscillator Figure 21 7 shows the equivalence circuit for a 32 768kHz oscillator OSC1 OSC2 Cs Ls Rs Co Figure 21 7 Equivalence Circuit for 32 768kHz Oscillator Handling pins when subclock not required If no subclock is required connect the OSC1 pin to Vss and leave OSC2 open as ...

Page 755: ... Resonator Since various characteristics related to the crystal resonator are closely linked to the user s board design thorough evaluation is necessary on the user s part for the F ZTAT version using the resonator connection examples shown in this section as a guide As the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit the ratings shoul...

Page 756: ...724 ...

Page 757: ...op mode 8 Software standby mode 9 Hardware standby mode 2 to 9 are low power dissipation states Sleep mode and sub sleep mode are CPU states medium speed mode is a CPU and bus master state sub active mode is a CPU and bus master and internal peripheral function state and module stop mode is an internal peripheral function including bus masters other than the CPU state Some of these states can be c...

Page 758: ... Halted Halted Halted ing speed operation ing retained retained retained retained retained reset PBC Function ing Medium speed operation Function ing Halted retained Halted retained Subclock operation Halted retained Halted retained Halted reset TPU Function Function Function Halted Halted Halted Halted Halted Halted PPG ing ing ing retained retained retained retained retained reset SCI0 Function ...

Page 759: ...Reset state High speed mode main clock Medium speed mode main clock Sub active mode subclock Sub sleep mode subclock Hardware standby mode Software standby mode Sleep mode main clock Watch mode subclock Notes 1 NMI IRQ0 to IRQ5 and WDT1 interrupts 2 NMI IRQ0 to IRQ5 IWDT0 interrupts and WDT1 interrupt 3 All interrupts 4 NMI and IRQ0 to IRQ5 When a transition is made between modes by means of an in...

Page 760: ...e Invoked by State SSBY PSS LSON DTON Instruction Interrupt High speed 0 0 Sleep High speed Medium speed Medium speed 0 1 1 0 0 Software standby High speed Medium speed 1 0 1 1 1 0 0 Watch High speed 1 1 1 0 Watch Sub active 1 1 0 1 1 1 1 1 Sub active Sub active 0 0 0 1 0 0 1 1 Sub sleep Sub active 1 0 1 1 0 0 Watch High speed 1 1 1 0 Watch Sub active 1 1 0 1 High speed 1 1 1 1 Don t care Do not s...

Page 761: ...viation R W Initial Value Address 1 Standby control register SBYCR R W H 58 H FDE4 System clock control register SCKCR R W H 00 H FDE6 Low power control register LPWRCR R W H 00 H FDEC Timer control status register WDT1 TCSR1 R W H 00 H FFA2 Module stop control register MSTPCRA R W H 3F H FDE8 A B C D MSTPCRB R W H FF H FDE9 MSTPCRC R W H FF H FDEA MSTPCRD R W B 11 H FC60 Note 1 Lower 16 bits of t...

Page 762: ... the SLEEP instruction the operating mode is determined in combination with other control bits Note that the value of the SSBY bit does not change even when shifting between modes using interrupts Bit 7 SSBY Description 0 Shifts to sleep mode when the SLEEP instruction is executed in high speed mode or medium speed mode Shifts to sub sleep mode when the SLEEP instruction is executed in sub active ...

Page 763: ...me 32768 states 1 Standby time 65536 states 1 0 0 Standby time 131072 states 1 Standby time 262144 states Initial value 1 0 Reserved 1 Standby time 16 states Bit 3 Output Port Enable OPE This bit specifies whether the output of the address bus and bus control signals AS RD HWR LWR is retained or set to high impedance state in the software standby mode watch mode and when making a direct transition...

Page 764: ... Bit 7 Description PSTOP High Speed Mode Medium Speed Mode Sub Active Mode Sleep Mode Sub Sleep Mode Software Standby Mode Watch Mode and Direct Transition Hardware Standby Mode 0 ø output initial value ø output Fixed high High impedance 1 Fixed high Fixed high Fixed high High impedance Bits 6 to 4 Reserved These bits are always read as 0 and cannot be modified Bit 3 Frequency Multiplication Facto...

Page 765: ... W 3 RFCUT 0 R W 0 STC0 0 R W 2 0 R W 1 STC1 0 R W Bit Initial value R W The LPWRCR is an 8 bit read write register that controls the low power dissipation modes The LPWRCR is initialized to H 00 at a reset and when in hardware standby mode It is not initialized in software standby mode The following describes bits 7 to 2 For details of other bits see section 21 2 2 Low Power Control Register LPWR...

Page 766: ...by executing the SLEEP instruction this bit specifies the operating mode in combination with other control bits This bit also controls whether to shift to high speed mode or sub active mode when watch mode is cancelled Bit 6 LSON Description 0 When the SLEEP instruction is executed in high speed mode or medium speed mode operation shifts to sleep mode software standby mode or watch mode When the S...

Page 767: ...1 Sampling using 1 4 xø Bit 4 Subclock enable SUBSTP This bit enables disables subclock generation Bit 4 SUBSTP Description 0 Enables subclock generation Initial value 1 Disables subclock generation Bit 3 Oscillation Circuit Feedback Resistance Control Bit RFCUT This bit turns the internal feedback resistance of the main clock oscillation circuit ON OFF Bit 3 RFCUT Description 0 When the main cloc...

Page 768: ...odes The operating mode selected after the SLEEP instruction is executed is determined in combination with other control bits For details see the description for clock selection in section 12 2 2 Timer Control Status Register TCSR and this section Bit 4 PSS Description 0 TCNT counts the divided clock from the ø based prescaler PSM When the SLEEP instruction is executed in high speed mode or medium...

Page 769: ...MSTPB2 MSTPB1 MSTPB0 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W MSTPCRC Bit 7 6 5 4 3 2 1 0 MSTPC7 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 Initial value 1 1 1 1 1 1 1 1 R W R W R W R W R W R W R W R W MSTPCRD Bit 7 6 5 4 3 2 1 0 MSTPD7 MSTPD6 Initial value 1 1 Undefined Undefined Undefined Undefined Undefined Undefined R W R W R W MSTPCR comprising four 8 bit readable writ...

Page 770: ...top mode is cleared initial value of MSTPA7 and MSTPA6 1 Module stop mode is set initial value of MSTPA5 to 0 MSTPB7 to 0 MSTPC7 to 0 and MSTPD7 6 22 3 Medium Speed Mode In high speed mode when the SCK2 to SCK0 bits in SCKCR are set to 1 the operating mode changes to medium speed mode as soon as the current bus cycle ends In medium speed mode the CPU operates on the operating clock ø 2 ø 4 ø 8 ø 1...

Page 771: ...n the case of a reset caused by overflow of the watchdog timer When the STBY pin is driven low a transition is made to hardware standby mode Figure 22 2 shows the timing for transition to and clearance of medium speed mode ø Bus master clock supporting module clock Internal address bus Internal write signal Medium speed mode SBYCR SBYCR Figure 22 2 Medium Speed Mode Transition and Clearance Timing...

Page 772: ... Stop Mode Module stop mode can be set for individual on chip supporting modules When the corresponding MSTP bit in MSTPCR is set to 1 module operation stops at the end of the bus cycle and a transition is made to module stop mode The CPU continues operating independently Table 22 4 shows MSTP bits and the corresponding on chip supporting modules When the corresponding MSTP bit is cleared to 0 mod...

Page 773: ...ge Notes DTC Module Stop Depending on the operating status of the DTC the MSTPA7 and MSTPA6 bits may not be set to 1 Setting of the DTC module stop mode should be carried out only when the respective module is not activated For details refer to section 8 Data Transfer Controller DTC On Chip Supporting Module Interrupt Relevant interrupt operations cannot be performed in module stop mode Consequent...

Page 774: ...en an NMI or IRQ0 to IRQ5 interrupt request signal is input clock oscillation starts and after the elapse of the time set in bits STS2 to STS0 in SYSCR stable clocks are supplied to the entire H8S 2646 Series chip software standby mode is cleared and interrupt exception handling is started When clearing software standby mode with an IRQ0 to IRQ5 interrupt set the corresponding enable bit to 1 and ...

Page 775: ... 0 131072 states 6 6 8 2 10 9 13 1 16 4 21 8 32 8 1 262144 states 13 1 16 4 21 8 26 2 32 8 43 6 65 6 1 0 Reserved µs 1 16 states 0 8 1 0 1 3 1 6 2 0 1 7 4 0 Recommended time setting Note Do not use this setting Using an External Clock The PLL circuit requires a time for stabilization Insert a wait of 2 ms min 22 6 4 Software Standby Mode Application Example Figure 22 3 shows an example in which a ...

Page 776: ...when a high level signal is output Current Dissipation during Oscillation Stabilization Wait Period Current dissipation increases during the oscillation stabilization wait period Write Data Buffer Function The write data buffer function and software standby mode cannot be used at the same time When the write data buffer function is used the WDBE bit in BCRL should be cleared to 0 to cancel the wri...

Page 777: ...ME bit in SYSCR should be cleared to 0 before driving the STBY pin low Do not change the state of the mode pins MD2 to MD0 while the H8S 2646 Series is in hardware standby mode Hardware standby mode is cleared by means of the STBY pin and the RES pin When the STBY pin is driven high while the RES pin is low the reset state is set and clock oscillation is started Ensure that the RES pin is held low...

Page 778: ...cillation stabilization time Reset exception handling Figure 22 4 Hardware Standby Mode Timing 22 8 Watch Mode 22 8 1 Watch Mode CPU operation makes a transition to watch mode when the SLEEP instruction is executed in high speed mode or sub active mode with SBYCR SSBY 1 LPWRCR DTON 0 and TCSR WDT1 PSS 1 In watch mode the CPU is stopped and supporting modules other than WDT1 are also stopped The co...

Page 779: ...o disable the reception of that interrupt or is masked by the CPU See section 22 6 3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode for how to set the oscillation stabilization time when making a transition from watch mode to high speed mode Exiting Watch Mode by RES pins For exiting watch mode by the RES pins see Clearing with the RES pins in section 22 6 2 Clearing S...

Page 780: ...al supporting modules NMI pin or IRQ0 to IRQ5 or signals at the RES or STBY pins Exiting Sub Sleep Mode by Interrupts When an interrupt occurs sub sleep mode is exited and interrupt exception processing starts In the case of IRQ0 to IRQ5 interrupts sub sleep mode is not cancelled if the corresponding enable bit has been cleared to 0 and in the case of interrupts from the internal supporting module...

Page 781: ...EEP instruction or the RES or STBY pins Exiting Sub Active Mode by SLEEP Instruction When the SLEEP instruction is executed with the SBYCR SSBY bit 1 LPWRCR DTON bit 0 and TCSR WDT1 PSS bit 1 the CPU exits sub active mode and a transition is made to watch mode When the SLEEP instruction is executed with the SBYCR SSBY bit 0 LPWRCR LSON bit 1 and TCSR WDT1 PSS bit 1 a transition is made to sub slee...

Page 782: ...R LSON bit 0 and DTON bit 1 and TSCR WDT1 PSS bit 1 to make a direct transition to high speed mode after the time set in SBYCR STS2 to STS0 has elapsed 22 12 ø Clock Output Disabling Function Output of the ø clock can be controlled by means of the PSTOP bit in SCKCR and DDR for the corresponding port When the PSTOP bit is set to 1 the ø clock stops at the end of the bus cycle and ø output goes hig...

Page 783: ...ode has been performed If a DTC activation source occurs in sub active mode the DTC will be activated only after module stop mode has been cleared and high speed mode or medium speed mode has been entered 2 The on chip peripheral modules DTC and TPU which halt operation in sub active mode cannot clear an interrupt in sub active mode Therefore if a transition is made to sub active mode while an int...

Page 784: ...752 ...

Page 785: ...ut voltage ports A B C D E ports PF2 PF4 to PF6 Vin 0 3 to LPVCC 0 3 V Input voltage ports H and J Vin 0 3 to PWMVCC 0 3 V Input voltage except ports 4 9 A B C D E ports PF2 PF4 to PF6 H and J Vin 0 3 to VCC 0 3 V Reference voltage Vref 0 3 to AVCC 0 3 V Analog power supply voltage AVCC 0 3 to 7 0 V Analog input voltage VAN 0 3 to AVCC 0 3 V Operating temperature Topr Regular specifications 20 to ...

Page 786: ...shown in figure 23 1 3 3 5 4 4 5 5 5 5 6 24 20 16 12 8 4 0 Operating range in high speed medium speed and sleep modes Frequency MHz Power supply voltage V 3 3 5 4 4 5 5 5 5 6 32 768 0 Operating range in watch sub active and sub sleep modes Frequency MHz Power supply voltage V Figure 23 1 Power Supply Voltage and Operating Ranges ...

Page 787: ...C to 85 C wide range specifications 1 Item Symbol Min Typ Max Unit Test Conditions Schmitt IRQ0 to IRQ5 VT 1 0 V trigger input VT VCC 0 7 voltage VT VT 0 4 Input high voltage RES STBY NMI FWE MD2 to MD0 VIH VCC 0 7 VCC 0 3 V EXTAL VCC 0 7 VCC 0 3 Ports 1 to 3 5 H J K Ports PF0 PF3 PF7 2 2 VCC 0 3 HRxD 2 2 VCC 0 3 Ports A to E Ports PF2 PF4 to PF6 2 2 LPVCC 0 3 Ports 4 9 AVCC 0 7 AVCC 0 3 Input low...

Page 788: ...6 3 5 IOH 1 mA PWM1A to 1H PWM2A to 2H PWMVCC 0 5 IOH 15 mA Output low voltage All output pins except PWM1A to PWM1H and PWM2A to PWM2H VOL 0 4 V IOL 1 6 mA PWM1A to 1H PWM2A to 2H 0 5 V IOL 15 mA Input leakage RES Iin 1 0 µA Vin current STBY NMI MD2 to MD0 1 0 0 5 to VCC 0 5 HRxD FWE 1 0 Ports 4 9 1 0 Vin 0 5 to AVCC 0 5 Three state leakage current off state Ports 1 to 3 5 H J K Ports PF0 PF3 PF7...

Page 789: ... 32 40 mA f 20 MHz reference values Subactive mode 130 220 µA Using 32 768 kHz crystal resonator Subsleep mode 95 160 µA Using 32 768 kHz crystal resonator Watch mode 15 60 µA Using 32 768 kHz crystal resonator Standby 2 0 10 µA Ta 50 C mode 3 80 50 C Ta LCD power supply port power supply current During operation LPlCC 10 20 mA Standby 0 1 10 µA Ta 50 C mode 3 80 50 C Ta Analog power supply curren...

Page 790: ...2 Current dissipation values are for VIH min VCC 0 5 V VIL max 0 5 V with all output pins unloaded and the on chip pull up resistors in the off state 3 The values are for VRAM LPVCC 3 0 V VIH min VCC 0 9 and VIL max 0 3 V 4 ICC depends on VCC and f as follows ICCmax 0 18 mA MHz V VCC f 2 87 mA MHz f 0 52 mA V VCC 0 8 mA at normal operation ICCmax 0 17 mA MHz V VCC f 2 13 mA MHz f 0 75 mA V VCC 0 3...

Page 791: ...missible output low current total Total of all output pins except PWM1A to PWM1H PWM2A to PWM2H IOL 80 mA Total of PWM1A to PWM1H PWM2A to PWM2H IOL 150 mA Ta 75 C to 85 C 180 mA Ta 25 C 220 mA Ta 40 C Permissible output high current per pin All output pins except PWM1A to PWM1H PWM2A to PWM2H IOH 2 0 mA PWM1A to PWM1H PWM2A to PWM2H IOH 25 mA Ta 75 C to 85 C 30 mA Ta 25 C 40 mA Ta 40 C Permissibl...

Page 792: ...racteristics 5 V RL RH C LSI output pin C 50 pF Ports A to F In case of expansion bus control signal output pin setting C 30 pF All ports except ports A to F RL 2 4 kΩ RH 12 kΩ Input output timing measurement levels Low level 0 8 V High level 2 0 V Figure 23 2 Output Load Circuit ...

Page 793: ...Item Symbol Min Max Unit Test Conditions Clock cycle time tcyc 50 250 ns Figure 23 3 Clock high pulse width tCH 25 ns Clock low pulse width tCL 25 ns Clock rise time tCr 10 ns Clock fall time tCf 10 ns Clock oscillator settling time at reset crystal tOSC1 20 ms Figure 23 4 Clock oscillator settling time in software standby crystal tOSC2 8 ms Figure 22 3 Sub clock oscillator settling time tOSC3 2 s...

Page 794: ...762 tCH tCf tcyc tCL tCr ø Figure 23 3 System Clock Timing tOSC1 tOSC1 VCC STBY RES ø Figure 23 4 Oscillator Settling Timing ...

Page 795: ...5 C regular specifications Ta 40 C to 85 C wide range specifications Condition Item Symbol Min Max Unit Test Conditions RES setup time tRESS 200 ns Figure 23 5 RES pulse width tRESW 20 tcyc NMI setup time tNMIS 150 ns Figure 23 6 NMI hold time tNMIH 10 NMI pulse width exiting software standby mode tNMIW 200 ns IRQ setup time tIRQS 150 ns IRQ hold time tIRQH 10 ns IRQ pulse width exiting software s...

Page 796: ...764 tRESW tRESS ø tRESS RES Figure 23 5 Reset Input Timing ø tIRQS IRQ Edge input tIRQH tNMIS tNMIH tIRQS IRQ Level input NMI IRQ tNMIW tIRQW Figure 23 6 Interrupt Input Timing ...

Page 797: ... delay time tASD 45 ns RD delay time 1 tRSD1 45 ns RD delay time 2 tRSD2 45 ns Read data setup time tRDS 20 ns Read data hold time tRDH 10 ns Read data access time 1 tACC1 1 0 tcyc 60 ns Read data access time 2 tACC2 1 5 tcyc 50 ns Read data access time 3 tACC3 2 0 tcyc 60 ns Read data access time 4 tACC4 2 5 tcyc 50 ns Read data access time 5 tACC5 3 0 tcyc 60 ns WR delay time 1 tWRD1 35 ns WR de...

Page 798: ... tAH tACC2 tRSD1 tASD tASD tAD tACC3 tRDH tWRD2 tWRD2 tWSW1 tWDD tWDH T1 T2 tAS tAS tAS tAH ø AS A23 to A0 RD read D15 to D0 read HWR LWR write D15 to D0 write tRDS Figure 23 7 Basic Bus Timing Two State Access ...

Page 799: ...S tAH tACC4 tRSD1 tASD tASD tAD tACC5 tRDH tWRD2 tWRD1 tWSW2 tWDD tWDH T1 T3 tWDS T2 tRDS tAS tAH ø AS A23 to A0 RD read D15 to D0 read HWR LWR write D15 to D0 write Figure 23 8 Basic Bus Timing Three State Access ...

Page 800: ...768 tWTH T1 T2 WAIT Tw T3 tWTS tWTH tWTS ø AS A23 to A0 RD read D15 to D0 read HWR LWR write D15 to D0 write Figure 23 9 Basic Bus Timing Three State Access with One Wait State ...

Page 801: ...769 tRSD2 tAS tAH tASD tASD tAD tACC3 tRDS tRDH T1 T2 T2 or T3 T1 ø AS A23 to A0 D15 to D0 read RD read Figure 23 10 Burst ROM Access Timing Two State Access ...

Page 802: ...770 ø T1 AS A23 to A0 T1 tACC1 D15 to D0 read T2 or T3 tRDH tAD RD read tRDS tRSD2 Figure 23 11 Burst ROM Access Timing One State Access ...

Page 803: ...0 C to 85 C wide range specifications Condition Item Symbol Min Max Unit Test Conditions I O port Output data delay time tF 50 ns Figure 23 12 Input data setup time tPRS 30 Input data hold time tPRH 30 PPG Pulse output delay time tPOD 50 ns Figure 23 13 TPU Timer output delay time tTOCD 50 ns Figure 23 14 Timer input setup time tTICD 30 Timer clock input setup time tTCKS 30 ns Figure 23 15 Timer c...

Page 804: ...ock rise time tSCKr 1 5 tcyc Input clock fall time tSCKf 1 5 Transmit data delay time tTXD 50 ns Figure 23 18 Receive data setup time synchronous tRXS 50 Receive data hold time synchronous tRXH 50 A D converter Trigger input setup time tTRGS 50 ns Figure 23 19 HCAN Transmit data delay time tHTXD 100 ns Figure 23 20 Transmit data setup time tHRXS 100 Transmit data hold time tHRXH 100 ...

Page 805: ... 5 9 A to F K read tPRS T1 T2 tPWD tPRH Port 1 to 3 5 A to F K write ø Port H J read Port H J write tPRS T3 T4 tPWD tPRH T1 T2 Figure 23 12 I O Port Input Output Timing ø PO15 to 8 tPOD Figure 23 13 PPG Output Timing ...

Page 806: ...e 23 14 TPU Input Output Timing tTCKS ø tTCKS TCLKA to TCLKD tTCKWH tTCKWL Figure 23 15 TPU Clock Input Timing ø PWM1A to PWM1H PWM2A to PWM2H tMPWMOD Figure 23 16 Motor Control PWM Output Timing H8S 2646 H8S 2646R H8S 2645 SCK0 SCK1 H8S 2648 H8S 2648R H8S 2647 SCK0 to SCK2 tSCKW tSCKr tSCKf tScyc Figure 23 17 SCK Clock Input Timing ...

Page 807: ... tRXS tRXH tTXD Figure 23 18 SCI Input Output Timing Clock Synchronous Mode ø ADTRG tTRGS Figure 23 19 A D Converter External Trigger Input Timing CK HTxD transmit data HRxD receive data tHTXD VOL VOL tHRXH tHRXS Preliminary Figure 23 20 HCAN Input Output Timing ...

Page 808: ... 5 5 V Vref 4 5 V to AVCC VSS PWMVSS PLLVSS AVSS 0 V Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Condition Item Min Typ Max Unit Resolution 10 10 10 bits Conversion time 13 3 µs Analog input capacitance 20 pF Permissible signal source impedance 5 kΩ Nonlinearity error 3 5 LSB Offset error 3 5 LSB Full scale error 3 5 LSB Quantization 0 5 LSB Absolute accuracy 4...

Page 809: ...Unit Notes Segment driver step down voltage VDS SEG1 to SEG24 H8S 2646 H8S 2646R H8S 2645 ID 2 µA 0 6 V 1 SEG1 to SEG40 H8S 2648 H8S 2648R H8S 2647 Common driver step down voltage VDC COM1 to COM4 ID 2 µA 0 3 V 1 LCD power supply division resistor RLCD Between V1 and VSS 40 300 1000 kΩ LCD voltage VLCD V1 4 5 LPVC C V 2 Notes 1 Voltage step down between power supply pins V1 V2 V3 and VSS and segme...

Page 810: ... 50 50 µs Wait time after P bit setting 1 4 tsp30 28 30 32 µs Programming time wait tsp200 198 200 202 µs Programming time wait tsp10 8 10 12 µs Additional programming time wait Wait time after P bit clear 1 tcp 5 5 µs Wait time after PSU bit clear 1 tcpsu 5 5 µs Wait time after PV bit setting 1 tspv 4 4 µs Wait time after H FF dummy write 1 tspvr 2 2 µs Wait time after PV bit clear 1 tcpv 2 2 µs ...

Page 811: ...ication time 4 To specify the maximum programming time value tP max in the 128 byte programming algorithm set the max value 1000 for the maximum programming count N The wait time after P bit setting should be changed as follows according to the value of the programming counter n Programming counter n 1 to 6 tsp30 30 µs Programming counter n 7 to 1000 tsp200 200 µs In additional programming Program...

Page 812: ...780 ...

Page 813: ...Z zero flag in CCR V V overflow flag in CCR C C carry flag in CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Add Subtract Multiply Divide Logical AND Logical OR Logical exclusive OR Transfer from the operand on the left to the operand on the right or transition from the state on the left to the state on the right Logical NOT logical complement Contents of operand 8 16...

Page 814: ...782 Condition Code Notation Symbol Changes according to the result of instruction Undetermined no guaranteed value 0 Always cleared to 0 1 Always set to 1 Not affected by execution of the instruction ...

Page 815: ...B Rs ERd B 2 MOV B Rs d 16 ERd B 4 MOV B Rs d 32 ERd B 8 MOV B Rs ERd B 2 MOV B Rs aa 8 B 2 MOV B Rs aa 16 B 4 MOV B Rs aa 32 B 6 MOV W xx 16 Rd W 4 MOV W Rs Rd W 2 MOV W ERs Rd W 2 xx 8 Rd8 0 1 Rs8 Rd8 0 1 ERs Rd8 0 2 d 16 ERs Rd8 0 3 d 32 ERs Rd8 0 5 ERs Rd8 ERs32 1 ERs32 0 3 aa 8 Rd8 0 2 aa 16 Rd8 0 3 aa 32 Rd8 0 4 Rs8 ERd 0 2 Rs8 d 16 ERd 0 3 Rs8 d 32 ERd 0 5 ERd32 1 ERd32 Rs8 ERd 0 3 Rs8 aa 8...

Page 816: ...OV L ERs ERd L 2 MOV L ERs ERd L 4 MOV L d 16 ERs ERd L 6 MOV L d 32 ERs ERd L 10 MOV L ERs ERd L 4 MOV L aa 16 ERd L 6 MOV L aa 32 ERd L 8 d 16 ERs Rd16 0 3 d 32 ERs Rd16 0 5 ERs Rd16 ERs32 2 ERs32 0 3 aa 16 Rd16 0 3 aa 32 Rd16 0 4 Rs16 ERd 0 2 Rs16 d 16 ERd 0 3 Rs16 d 32 ERd 0 5 ERd32 2 ERd32 Rs16 ERd 0 3 Rs16 aa 16 0 3 Rs16 aa 32 0 4 xx 32 ERd32 0 3 ERs32 ERd32 0 1 ERs ERd32 0 4 d 16 ERs ERd32 ...

Page 817: ...Rn L 4 LDM SP ERm ERn L 4 STM ERm ERn SP L 4 MOVFPE aa 16 Rd MOVTPE Rs aa 16 ERs32 ERd 0 4 ERs32 d 16 ERd 0 5 ERs32 d 32 ERd 0 7 ERd32 4 ERd32 ERs32 ERd 0 5 ERs32 aa 16 0 5 ERs32 aa 32 0 6 SP Rn16 SP 2 SP 0 3 SP ERn32 SP 4 SP 0 5 SP 2 SP Rn16 SP 0 3 SP 4 SP ERn32 SP 0 5 SP ERn32 SP 4 SP 7 9 11 1 Repeated for each register restored SP 4 SP ERn32 SP 7 9 11 1 Repeated for each register saved 2 2 Oper...

Page 818: ...ADDS 4 ERd L 2 INC B Rd B 2 INC W 1 Rd W 2 INC W 2 Rd W 2 INC L 1 ERd L 2 INC L 2 ERd L 2 DAA Rd B 2 SUB B Rs Rd B 2 SUB W xx 16 Rd W 4 Rd8 xx 8 Rd8 1 Rd8 Rs8 Rd8 1 Rd16 xx 16 Rd16 3 2 Rd16 Rs16 Rd16 3 1 ERd32 xx 32 ERd32 4 3 ERd32 ERs32 ERd32 4 1 Rd8 xx 8 C Rd8 5 1 Rd8 Rs8 C Rd8 5 1 ERd32 1 ERd32 1 ERd32 2 ERd32 1 ERd32 4 ERd32 1 Rd8 1 Rd8 1 Rd16 1 Rd16 1 Rd16 2 Rd16 1 ERd32 1 ERd32 1 ERd32 2 ERd...

Page 819: ...Rd B 2 MULXU B Rs Rd B 2 MULXU W Rs ERd W 2 MULXS B Rs Rd B 4 MULXS W Rs ERd W 4 Rd16 Rs16 Rd16 3 1 ERd32 xx 32 ERd32 4 3 ERd32 ERs32 ERd32 4 1 Rd8 xx 8 C Rd8 5 1 Rd8 Rs8 C Rd8 5 1 ERd32 1 ERd32 1 ERd32 2 ERd32 1 ERd32 4 ERd32 1 Rd8 1 Rd8 1 Rd16 1 Rd16 1 Rd16 2 Rd16 1 ERd32 1 ERd32 1 ERd32 2 ERd32 1 Rd8 decimal adjust Rd8 1 Rd8 Rs8 Rd16 unsigned multiplication 12 Rd16 Rs16 ERd32 20 unsigned multip...

Page 820: ...ERd L 2 EXTU W Rd W 2 EXTU L ERd L 2 Rd16 Rs8 Rd16 RdH remainder 6 7 12 RdL quotient unsigned division ERd32 Rs16 ERd32 Ed remainder 6 7 20 Rd quotient unsigned division Rd16 Rs8 Rd16 RdH remainder 8 7 13 RdL quotient signed division ERd32 Rs16 ERd32 Ed remainder 8 7 21 Rd quotient signed division Rd8 xx 8 1 Rd8 Rs8 1 Rd16 xx 16 3 2 Rd16 Rs16 3 1 ERd32 xx 32 4 3 ERd32 ERs32 4 1 0 Rd8 Rd8 1 0 Rd16 ...

Page 821: ...AC LDMAC ERs MACH LDMAC ERs MACL STMAC MACH ERd STMAC MACL ERd bit 7 of Rd16 0 1 bit 15 to 8 of Rd16 bit 15 of ERd32 0 1 bit 31 to 16 of ERd32 ERd 0 CCR set 1 0 4 bit 7 of ERd ERnx ERm MAC MAC 4 signal multiplication 11 11 11 ERn 2 ERn ERm 2 ERm 0 MACH MACL 2 12 ERs MACH 2 12 ERs MACL 2 12 MACH ERd 1 12 MACL ERd 1 12 Operation Condition Code I H N Z V C Advanced No of States 1 L L L L 2 2 2 2 2 ...

Page 822: ...Rs Rd B 2 XOR W xx 16 Rd W 4 XOR W Rs Rd W 2 XOR L xx 32 ERd L 6 XOR L ERs ERd L 4 NOT B Rd B 2 NOT W Rd W 2 NOT L ERd L 2 Rd8 xx 8 Rd8 0 1 Rd8 Rs8 Rd8 0 1 Rd16 xx 16 Rd16 0 2 Rd16 Rs16 Rd16 0 1 ERd32 xx 32 ERd32 0 3 ERd32 ERs32 ERd32 0 2 Rd8 xx 8 Rd8 0 1 Rd8 Rs8 Rd8 0 1 Rd16 xx 16 Rd16 0 2 Rd16 Rs16 Rd16 0 1 ERd32 xx 32 ERd32 0 3 ERd32 ERs32 ERd32 0 2 Rd8 xx 8 Rd8 0 1 Rd8 Rs8 Rd8 0 1 Rd16 xx 16 R...

Page 823: ...HAL W 2 Rd W 2 SHAL L ERd L 2 SHAL L 2 ERd L 2 SHAR B Rd B 2 SHAR B 2 Rd B 2 SHAR W Rd W 2 SHAR W 2 Rd W 2 SHAR L ERd L 2 SHAR L 2 ERd L 2 SHLL B Rd B 2 SHLL B 2 Rd B 2 SHLL W Rd W 2 SHLL W 2 Rd W 2 SHLL L ERd L 2 SHLL L 2 ERd L 2 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Operation Condition Code I H N Z V C Advanced No of States 1 C MSB LSB MSB LSB 0 C MSB LSB C 0 ...

Page 824: ... 2 SHLR L 2 ERd L 2 ROTXL B Rd B 2 ROTXL B 2 Rd B 2 ROTXL W Rd W 2 ROTXL W 2 Rd W 2 ROTXL L ERd L 2 ROTXL L 2 ERd L 2 ROTXR B Rd B 2 ROTXR B 2 Rd B 2 ROTXR W Rd W 2 ROTXR W 2 Rd W 2 ROTXR L ERd L 2 ROTXR L 2 ERd L 2 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Operation Condition Code I H N Z V C Advanced No of States 1 C MSB LSB 0 C MSB LSB C MSB LSB ...

Page 825: ...n ERn d ERn ERn ERn aa d PC aa Mnemonic ROTL ROTR ROTL B Rd B 2 ROTL B 2 Rd B 2 ROTL W Rd W 2 ROTL W 2 Rd W 2 ROTL L ERd L 2 ROTL L 2 ERd L 2 ROTR B Rd B 2 ROTR B 2 Rd B 2 ROTR W Rd W 2 ROTR W 2 Rd W 2 ROTR L ERd L 2 ROTR L 2 ERd L 2 Operation Condition Code I H N Z V C Advanced No of States 1 C MSB LSB C MSB LSB ...

Page 826: ...xx 3 Rd B 2 BCLR xx 3 ERd B 4 BCLR xx 3 aa 8 B 4 BCLR xx 3 aa 16 B 6 BCLR xx 3 aa 32 B 8 BCLR Rn Rd B 2 BCLR Rn ERd B 4 BCLR Rn aa 8 B 4 BCLR Rn aa 16 B 6 xx 3 of Rd8 1 1 xx 3 of ERd 1 4 xx 3 of aa 8 1 4 xx 3 of aa 16 1 5 xx 3 of aa 32 1 6 Rn8 of Rd8 1 1 Rn8 of ERd 1 4 Rn8 of aa 8 1 4 Rn8 of aa 16 1 5 Rn8 of aa 32 1 6 xx 3 of Rd8 0 1 xx 3 of ERd 0 4 xx 3 of aa 8 0 4 xx 3 of aa 16 0 5 xx 3 of aa 32...

Page 827: ...Rn aa 32 B 8 BTST xx 3 Rd B 2 BTST xx 3 ERd B 4 BTST xx 3 aa 8 B 4 BTST xx 3 aa 16 B 6 Rn8 of aa 32 0 6 xx 3 of Rd8 xx 3 of Rd8 1 xx 3 of ERd 4 xx 3 of ERd xx 3 of aa 8 4 xx 3 of aa 8 xx 3 of aa 16 5 xx 3 of aa 16 xx 3 of aa 32 6 xx 3 of aa 32 Rn8 of Rd8 Rn8 of Rd8 1 Rn8 of ERd Rn8 of ERd 4 Rn8 of aa 8 Rn8 of aa 8 4 Rn8 of aa 16 5 Rn8 of aa 16 Rn8 of aa 32 6 Rn8 of aa 32 xx 3 of Rd8 Z 1 xx 3 of ER...

Page 828: ... xx 3 Rd B 2 BILD xx 3 ERd B 4 BILD xx 3 aa 8 B 4 BILD xx 3 aa 16 B 6 BILD xx 3 aa 32 B 8 BST xx 3 Rd B 2 BST xx 3 ERd B 4 BST xx 3 aa 8 B 4 xx 3 of aa 32 Z 5 Rn8 of Rd8 Z 1 Rn8 of ERd Z 3 Rn8 of aa 8 Z 3 Rn8 of aa 16 Z 4 Rn8 of aa 32 Z 5 xx 3 of Rd8 C 1 xx 3 of ERd C 3 xx 3 of aa 8 C 3 xx 3 of aa 16 C 4 xx 3 of aa 32 C 5 xx 3 of Rd8 C 1 xx 3 of ERd C 3 xx 3 of aa 8 C 3 xx 3 of aa 16 C 4 xx 3 of a...

Page 829: ...32 B 8 BIAND xx 3 Rd B 2 BIAND xx 3 ERd B 4 BIAND xx 3 aa 8 B 4 BIAND xx 3 aa 16 B 6 BIAND xx 3 aa 32 B 8 BOR xx 3 Rd B 2 BOR xx 3 ERd B 4 C xx 3 of aa 16 5 C xx 3 of aa 32 6 C xx 3 of Rd8 1 C xx 3 of ERd 4 C xx 3 of aa 8 4 C xx 3 of aa 16 5 C xx 3 of aa 32 6 C xx 3 of Rd8 C 1 C xx 3 of ERd C 3 C xx 3 of aa 8 C 3 C xx 3 of aa 16 C 4 C xx 3 of aa 32 C 5 C xx 3 of Rd8 C 1 C xx 3 of ERd C 3 C xx 3 of...

Page 830: ...3 aa 16 B 6 BXOR xx 3 aa 32 B 8 BIXOR xx 3 Rd B 2 BIXOR xx 3 ERd B 4 BIXOR xx 3 aa 8 B 4 BIXOR xx 3 aa 16 B 6 BIXOR xx 3 aa 32 B 8 C xx 3 of aa 8 C 3 C xx 3 of aa 16 C 4 C xx 3 of aa 32 C 5 C xx 3 of Rd8 C 1 C xx 3 of ERd C 3 C xx 3 of aa 8 C 3 C xx 3 of aa 16 C 4 C xx 3 of aa 32 C 5 C xx 3 of Rd8 C 1 C xx 3 of ERd C 3 C xx 3 of aa 8 C 3 C xx 3 of aa 16 C 4 C xx 3 of aa 32 C 5 C xx 3 of Rd8 C 1 C ...

Page 831: ... Z 1 2 3 V 0 2 3 Operation Condition Code Branching Condition I H N Z V C Advanced No of States 1 BRA d 8 BT d 8 2 if condition is true then BRA d 16 BT d 16 4 PC PC d BRN d 8 BF d 8 2 else next BRN d 16 BF d 16 4 BHI d 8 2 BHI d 16 4 BLS d 8 2 BLS d 16 4 BCC d B BHS d 8 2 BCC d 16 BHS d 16 4 BCS d 8 BLO d 8 2 BCS d 16 BLO d 16 4 BNE d 8 2 BNE d 16 4 BEQ d 8 2 BEQ d 16 4 BVC d 8 2 BVC d 16 4 ...

Page 832: ...c Bcc V 1 2 3 N 0 2 3 N 1 2 3 N V 0 2 3 N V 1 2 3 Z N V 0 2 3 Z N V 1 2 3 Operation Condition Code Branching Condition I H N Z V C Advanced No of States 1 BVS d 8 2 BVS d 16 4 BPL d 8 2 BPL d 16 4 BMI d 8 2 BMI d 16 4 BGE d 8 2 BGE d 16 4 BLT d 8 2 BLT d 16 4 BGT d 8 2 BGT d 16 4 BLE d 8 2 BLE d 16 4 ...

Page 833: ...monic JMP BSR JSR RTS JMP ERn 2 JMP aa 24 4 JMP aa 8 2 BSR d 8 2 BSR d 16 4 JSR ERn 2 JSR aa 24 4 JSR aa 8 2 RTS 2 PC ERn 2 PC aa 24 3 PC aa 8 5 PC SP PC PC d 8 4 PC SP PC PC d 16 5 PC SP PC ERn 4 PC SP PC aa 24 5 PC SP PC aa 8 6 PC SP 5 Operation Condition Code I H N Z V C Advanced No of States 1 ...

Page 834: ... d 32 ERs CCR W 10 LDC d 32 ERs EXR W 10 LDC ERs CCR W 4 LDC ERs EXR W 4 LDC aa 16 CCR W 6 LDC aa 16 EXR W 6 LDC aa 32 CCR W 8 LDC aa 32 EXR W 8 PC SP CCR SP 1 8 9 EXR SP vector PC EXR SP CCR SP 5 9 PC SP Transition to power down state 2 xx 8 CCR 1 xx 8 EXR 2 Rs8 CCR 1 Rs8 EXR 1 ERs CCR 3 ERs EXR 3 d 16 ERs CCR 4 d 16 ERs EXR 4 d 32 ERs CCR 6 d 32 ERs EXR 6 ERs CCR ERs32 2 ERs32 4 ERs EXR ERs32 2 ...

Page 835: ... STC EXR aa 16 W 6 STC CCR aa 32 W 8 STC EXR aa 32 W 8 ANDC xx 8 CCR B 2 ANDC xx 8 EXR B 4 ORC xx 8 CCR B 2 ORC xx 8 EXR B 4 XORC xx 8 CCR B 2 XORC xx 8 EXR B 4 NOP 2 CCR Rd8 1 EXR Rd8 1 CCR ERd 3 EXR ERd 3 CCR d 16 ERd 4 EXR d 16 ERd 4 CCR d 32 ERd 6 EXR d 32 ERd 6 ERd32 2 ERd32 CCR ERd 4 ERd32 2 ERd32 EXR ERd 4 CCR aa 16 4 EXR aa 16 4 CCR aa 32 5 EXR aa 32 5 CCR xx 8 CCR 1 EXR xx 8 EXR 2 CCR xx ...

Page 836: ...sed in this LSI 3 Set to 1 when a carry or borrow occurs at bit 11 otherwise cleared to 0 4 Set to 1 when a carry or borrow occurs at bit 27 otherwise cleared to 0 5 Retains its previous value when the result is zero otherwise cleared to 0 6 Set to 1 when the divisor is negative otherwise cleared to 0 7 Set to 1 when the divisor is zero otherwise cleared to 0 8 Set to 1 when the quotient is negati...

Page 837: ...805 A 2 Instruction Codes Table A 2 shows the instruction codes ...

Page 838: ...16 BF d 16 Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion ADD ADDS ADDX AND ANDC BAND Bcc B B W W L L L L L B B B B W W L L B B B B B B B 1 0 0 ers IMM erd 0 0 0 0 0 0 erd erd erd erd erd erd ers IMM IMM 0 erd 0 IMM 0 IMM 0 0 0 8 0 7 0 7 0 0 0 0 9 0 E 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 rd 8 9 9 A A B B B rd E rd...

Page 839: ...E d 8 BLE d 16 Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion Bcc 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 8 A 8 B 8 C 8 D 8 E 8 F 8 2 3 4 5 6 7 8 9 A B C D E F disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp...

Page 840: ...byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion BCLR BIAND BILD BIOR B B B B B B B B B B B B B B B B B B B B B B B B B 0 0 0 1 0 1 0 1 0 IMM erd erd IMM erd IMM erd IMM erd 0 1 1 1 IMM IMM IMM IMM 0 1 1 1 IMM IMM IMM IMM 7 7 7 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 2 D F A A 2 D F A A 6 C E A A 7 C E A A 4 C E A A 1 3 rn 1 3 1 3 1 3 1 3 rd 0 8 8 rd 0 8 8 rd 0 0 0 rd 0 0 0 rd 0...

Page 841: ...te 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion BIST BIXOR BLD BNOT B B B B B B B B B B B B B B B B B B B B B B B B B 1 0 1 0 0 0 0 0 0 IMM erd IMM erd IMM erd IMM erd erd IMM IMM IMM IMM IMM IMM IMM IMM 1 1 0 0 IMM IMM IMM IMM 1 1 0 0 IMM IMM IMM IMM 1 1 1 1 0 0 0 0 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 7 D F A A 5 C E A A 7 C E A A 1 D F A A 1 D F A A 1 3 1 3 1 3 1 3 rn...

Page 842: ... byte 8th byte 9th byte 10th byte Instruc tion BOR BSET BSR BST BTST B B B B B B B B B B B B B B B B B B B B B B B B B B B 0 0 0 0 0 0 0 0 0 0 IMM erd IMM erd erd IMM erd IMM erd erd abs abs abs disp abs abs IMM IMM IMM IMM IMM IMM IMM IMM 0 0 0 0 IMM IMM IMM IMM 0 0 0 0 IMM IMM IMM IMM 0 0 0 0 0 0 0 0 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 5 5 6 7 7 6 6 7 7 7 6 6 6 7 4 C E A A 0 D F A A 0 D F A A 5 C 7 D ...

Page 843: ...byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion BTST BXOR CLRMAC CMP DAA DAS DEC DIVXS DIVXU EEPMOV B B B B B B B B B B W W L L B B B W W L L B W B W 0 0 1 IMM erd ers 0 0 0 0 0 erd erd erd erd erd IMM IMM 0 erd 0 IMM 0 IMM 0 0 7 6 6 7 7 7 6 6 0 A 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 E A A 5 C E A A 1 rd C 9 D A F F F A B B B B 1 1 1 3 B B 1 3 1 3 A rs 2 r...

Page 844: ...nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion EXTS EXTU INC JMP JSR LDC W L W L B W W L L B B B B W W W W W W W W W W 0 0 ern ern 0 0 0 0 erd erd erd erd ers ers ers ers ers ers ers ers 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 7 7 7 A B B B B 9 A B D E F 7 1 3 3 1 1 1 1 1 1 1 1 1 1 D F 5 7 0 5 D 7 F 4 0 1 4 4 4 4 4 ...

Page 845: ...Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion LDC LDM LDMAC MAC MOV W W L L L L L B B B B B B B B B B B B B B B B W W W W W 0 0 0 0 1 1 0 1 0 0 0 ers ers ers ers erd erd erd erd ers ers ers 0 0 ers ers erm 0 0 0 0 ern 1 ern 2 ern 3 erm 0 0 0 0 0 0 0 0 0 F 0 6 6 7 6 2 6 6 6 6 7 6 3 6 6 7 0 6 6 7 1 1 1 1 1 3 3...

Page 846: ...byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion MOV MOVFPE MOVTPE MULXS MULXU W W W W W W W W W L L L L L L L L L L L L L L B B B W B W 0 1 1 0 1 1 ers erd erd erd erd ers 0 0 0 erd erd erd ers ers ers ers erd erd erd erd 0 0 0 0 0 0 0 0 0 0 0 erd erd erd erd erd ers ers ers ers ers erd 0 0 erd ers 0 0 0 0 1 1 0 1 6 6 6 6 6 7 6 6 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 5 D B B 9 F 8 D ...

Page 847: ...struction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion NEG NOP NOT OR ORC POP PUSH ROTL B W L B W L B B W W L L B B W L W L B B W W L L 0 0 0 0 0 erd erd erd erd erd 1 1 1 0 1 1 1 C 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 7 7 7 0 7 7 7 rd 4 9 4 A 1 4 1 D 1 D 1 2 2 2 2 2 2 8 9 B 0 0 1 3 rs 4 rs 4 F 4 7 0 F 0 8 C 9 D B F rd rd 0 rd rd rd rd...

Page 848: ... SHAL L 2 ERd Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion ROTR ROTXL ROTXR RTE RTS SHAL B B W W L L B B W W L L B B W W L L B B W W L L 0 0 0 0 0 0 0 0 erd erd erd erd erd erd erd erd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 3 3 3 3 3 3 2 2 2 2 2 2 3 3 3 3 3 3 6 4 0 0 0 0 0 0 8 C 9 D B F 0 4 1 5...

Page 849: ...on Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion SHAR SHLL SHLR SLEEP STC B B W W L L B B W W L L B B W W L L B B W W W W W W W W 0 0 0 0 0 0 erd erd erd erd erd erd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 8 C 9 D B F 0 4 1 5 3 7 0 4 1 5 3 7 8 0 1 4 4 4 4 4 4...

Page 850: ...n Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion STC STM STMAC SUB SUBS SUBX TAS TRAPA XOR XORC W W W W L L L L L B W W L L L L L B B B B B W W L L B B 1 00 ers IMM 0 0 0 0 0 0 0 0 ers ers erd erd erd erd erd erd erd ers 0 0 0 0 ern ern ern erd 0 0 0 0 0 0 0 0 0 0 0 1 7 1 7 1 1 1 1 B 1 0 5 D 1 7 6 7 0 0 0 1 1 1 1 1 1 1 2 2 8 9 9 A A B...

Page 851: ...registers as follows Immediate data 2 3 8 16 or 32 bits Absolute address 8 16 24 or 32 bits Displacement 8 16 or 32 bits Register field 4 bits specifying an 8 bit or 16 bit register The symbols rs rd and rn correspond to operand symbols Rs Rd and Rn Register field 3 bits specifying an address register or 32 bit register The symbols ers erd ern and erm correspond to operand symbols ERs ERd ERn and ...

Page 852: ...S DIVXU BTST STC STMAC LDC LDMAC 4 ORC OR BCC RTS OR BOR BIOR 6 ANDC AND BNE RTE AND 5 XORC XOR BCS BSR XOR BXOR BIXOR BAND BIAND 7 LDC BEQ TRAPA BST BIST BLD BILD 8 BVC MOV 9 BVS A BPL JMP B BMI EEPMOV C BGE BSR D BLT MOV E ADDX SUBX BGT JSR F BLE MOV B ADD ADDX CMP SUBX OR XOR AND MOV ADD SUB MOV MOV CMP Table A 3 2 Table A 3 2 Table A 3 2 Table A 3 2 Table A 3 2 Table A 3 2 Table A 3 2 Table A ...

Page 853: ... ROTXR BCC MOVFPE OR OR 5 INC EXTU DEC BCS XOR XOR 6 MAC BNE AND AND 7 INC SHLL SHLR ROTXL ROTXR EXTU DEC BEQ LDC STC 8 SLEEP BVC MOV ADDS SHAL SHAR ROTL ROTR NEG SUBS 9 BVS A CLRMAC BPL MOV B NEG BMI ADD MOV SUB CMP C SHAL SHAR ROTL ROTR BGE MOVTPE D INC EXTS DEC BLT E TAS BGT F INC SHAL SHAR ROTL ROTR EXTS DEC BLE BH AH AL Table A 3 3 Table A 3 3 Table A 3 3 Table A 3 4 Table A 3 4 Table A 3 Ope...

Page 854: ...when most significant bit of DH is 1 Notes AH AL BH BL CH CL 01C05 01D05 01F06 7Cr06 1 7Cr07 1 7Dr06 1 7Dr07 1 7Eaa6 2 7Eaa7 2 7Faa6 2 7Faa7 2 0 MULXS BSET BSET BSET BSET 1 DIVXS BNOT BNOT BNOT BNOT 2 MULXS BCLR BCLR BCLR BCLR 3 DIVXS BTST BTST BTST BTST 4 OR 5 XOR 6 AND 7 8 9 A B C D E F 1 2 BOR BIOR BXOR BIXOR BAND BIAND BLD BILD BST BIST BOR BIOR BXOR BIXOR BAND BIAND BLD BILD BST BIST Table A ...

Page 855: ... is 0 Instruction when most significant bit of HH is 1 Note aa is the absolute address specification 5th byte 6th byte EH EL FH FL 7th byte 8th byte GH GL HH HL 6A10aaaa6 6A10aaaa7 6A18aaaa6 6A18aaaa7 AHALBHBLCHCLDHDLEH EL 0 BSET 1 BNOT 2 BCLR 3 BTST BOR BIOR BXOR BIXOR BAND BIAND BLD BILD BST BIST 4 5 6 7 8 9 A B C D E F 6A30aaaaaaaa6 6A30aaaaaaaa7 6A38aaaaaaaa6 6A38aaaaaaaa7 AHALBHBL FHFLGH GL 0...

Page 856: ...ecution of an instruction can be calculated from these two tables as follows Execution states I SI J SJ K SK L SL M SM N SN Examples Advanced mode program code and stack located in external memory on chip supporting modules accessed in two states with 8 bit bus width external devices accessed in three states with one wait state and 16 bit bus width 1 BSET 0 FFFFC7 8 From table A 5 I L 2 J K M N 0 ...

Page 857: ...hip Memory 8 Bit Bus 16 Bit Bus 2 State Access 3 State Access 2 State Access 3 State Access Instruction fetch SI 1 4 2 4 6 2m 2 3 m Branch address read SJ Stack operation SK Byte data access SL 2 2 3 m Word data access SM 4 4 6 2m Internal operation SN 1 1 1 1 1 1 1 Legend m Number of wait states inserted into external device access ...

Page 858: ...DD L xx 32 ERd 3 ADD L ERs ERd 1 ADDS ADDS 1 2 4 ERd 1 ADDX ADDX xx 8 Rd 1 ADDX Rs Rd 1 AND AND B xx 8 Rd 1 AND B Rs Rd 1 AND W xx 16 Rd 2 AND W Rs Rd 1 AND L xx 32 ERd 3 AND L ERs ERd 2 ANDC ANDC xx 8 CCR 1 ANDC xx 8 EXR 2 BAND BAND xx 3 Rd 1 BAND xx 3 ERd 2 1 BAND xx 3 aa 8 2 1 BAND xx 3 aa 16 3 1 BAND xx 3 aa 32 4 1 Bcc BRA d 8 BT d 8 2 BRN d 8 BF d 8 2 BHI d 8 2 BLS d 8 2 BCC d 8 BHS d 8 2 BCS...

Page 859: ...T d 16 2 1 BRN d 16 BF d 16 2 1 BHI d 16 2 1 BLS d 16 2 1 BCC d 16 BHS d 16 2 1 BCS d 16 BLO d 16 2 1 BNE d 16 2 1 BEQ d 16 2 1 BVC d 16 2 1 BVS d 16 2 1 BPL d 16 2 1 BMI d 16 2 1 BGE d 16 2 1 BLT d 16 2 1 BGT d 16 2 1 BLE d 16 2 1 BCLR BCLR xx 3 Rd 1 BCLR xx 3 ERd 2 2 BCLR xx 3 aa 8 2 2 BCLR xx 3 aa 16 3 2 BCLR xx 3 aa 32 4 2 BCLR Rn Rd 1 BCLR Rn ERd 2 2 BCLR Rn aa 8 2 2 BCLR Rn aa 16 3 2 BCLR Rn...

Page 860: ...1 BILD xx 3 ERd 2 1 BILD xx 3 aa 8 2 1 BILD xx 3 aa 16 3 1 BILD xx 3 aa 32 4 1 BIOR BIOR xx 8 Rd 1 BIOR xx 8 ERd 2 1 BIOR xx 8 aa 8 2 1 BIOR xx 8 aa 16 3 1 BIOR xx 8 aa 32 4 1 BIST BIST xx 3 Rd 1 BIST xx 3 ERd 2 2 BIST xx 3 aa 8 2 2 BIST xx 3 aa 16 3 2 BIST xx 3 aa 32 4 2 BIXOR BIXOR xx 3 Rd 1 BIXOR xx 3 ERd 2 1 BIXOR xx 3 aa 8 2 1 BIXOR xx 3 aa 16 3 1 BIXOR xx 3 aa 32 4 1 BLD BLD xx 3 Rd 1 BLD xx...

Page 861: ...OT Rn ERd 2 2 BNOT Rn aa 8 2 2 BNOT Rn aa 16 3 2 BNOT Rn aa 32 4 2 BOR BOR xx 3 Rd 1 BOR xx 3 ERd 2 1 BOR xx 3 aa 8 2 1 BOR xx 3 aa 16 3 1 BOR xx 3 aa 32 4 1 BSET BSET xx 3 Rd 1 BSET xx 3 ERd 2 2 BSET xx 3 aa 8 2 2 BSET xx 3 aa 16 3 2 BSET xx 3 aa 32 4 2 BSET Rn Rd 1 BSET Rn ERd 2 2 BSET Rn aa 8 2 2 BSET Rn aa 16 3 2 BSET Rn aa 32 4 2 BSR BSR d 8 2 2 BSR d 16 2 2 1 BST BST xx 3 Rd 1 BST xx 3 ERd 2...

Page 862: ...Rd 1 BTST Rn ERd 2 1 BTST Rn aa 8 2 1 BTST Rn aa 16 3 1 BTST Rn aa 32 4 1 BXOR BXOR xx 3 Rd 1 BXOR xx 3 ERd 2 1 BXOR xx 3 aa 8 2 1 BXOR xx 3 aa 16 3 1 BXOR xx 3 aa 32 4 1 CLRMAC CLRMAC 1 1 1 CMP CMP B xx 8 Rd 1 CMP B Rs Rd 1 CMP W xx 16 Rd 2 CMP W Rs Rd 1 CMP L xx 32 ERd 3 CMP L ERs ERd 1 DAA DAA Rd 1 DAS DAS Rd 1 DEC DEC B Rd 1 DEC W 1 2 Rd 1 DEC L 1 2 ERd 1 DIVXS DIVXS B Rs Rd 2 11 DIVXS W Rs ER...

Page 863: ...1 EXTU L ERd 1 INC INC B Rd 1 INC W 1 2 Rd 1 INC L 1 2 ERd 1 JMP JMP ERn 2 JMP aa 24 2 1 JMP aa 8 2 2 1 JSR JSR ERn 2 2 JSR aa 24 2 2 1 JSR aa 8 2 2 2 LDC LDC xx 8 CCR 1 LDC xx 8 EXR 2 LDC Rs CCR 1 LDC Rs EXR 1 LDC ERs CCR 2 1 LDC ERs EXR 2 1 LDC d 16 ERs CCR 3 1 LDC d 16 ERs EXR 3 1 LDC d 32 ERs CCR 5 1 LDC d 32 ERs EXR 5 1 LDC ERs CCR 2 1 1 LDC ERs EXR 2 1 1 LDC aa 16 CCR 3 1 LDC aa 16 EXR 3 1 L...

Page 864: ...Rn ERm 2 2 MOV MOV B xx 8 Rd 1 MOV B Rs Rd 1 MOV B ERs Rd 1 1 MOV B d 16 ERs Rd 2 1 MOV B d 32 ERs Rd 4 1 MOV B ERs Rd 1 1 1 MOV B aa 8 Rd 1 1 MOV B aa 16 Rd 2 1 MOV B aa 32 Rd 3 1 MOV B Rs ERd 1 1 MOV B Rs d 16 ERd 2 1 MOV B Rs d 32 ERd 4 1 MOV B Rs ERd 1 1 1 MOV B Rs aa 8 1 1 MOV B Rs aa 16 2 1 MOV B Rs aa 32 3 1 MOV W xx 16 Rd 2 MOV W Rs Rd 1 MOV W ERs Rd 1 1 MOV W d 16 ERs Rd 2 1 MOV W d 32 ER...

Page 865: ...L ERs ERd 2 2 MOV L d 16 ERs ERd 3 2 MOV L d 32 ERs ERd 5 2 MOV L ERs ERd 2 2 1 MOV L aa 16 ERd 3 2 MOV L aa 32 ERd 4 2 MOV L ERs ERd 2 2 MOV L ERs d 16 ERd 3 2 MOV L ERs d 32 ERd 5 2 MOV L ERs ERd 2 2 1 MOV L ERs aa 16 3 2 MOV L ERs aa 32 4 2 MOVFPE MOVFPE aa 16 Rd Can not be used in this LSI MOVTPE MOVTPE Rs aa 16 MULXS MULXS B Rs Rd 2 2 MULXS W Rs ERd 2 3 MULXU MULXU B Rs Rd 1 2 MULXU W Rs ERd ...

Page 866: ... 1 OR L xx 32 ERd 3 OR L ERs ERd 2 ORC ORC xx 8 CCR 1 ORC xx 8 EXR 2 POP POP W Rn 1 1 1 POP L ERn 2 2 1 PUSH PUSH W Rn 1 1 1 PUSH L ERn 2 2 1 ROTL ROTL B Rd 1 ROTL B 2 Rd 1 ROTL W Rd 1 ROTL W 2 Rd 1 ROTL L ERd 1 ROTL L 2 ERd 1 ROTR ROTR B Rd 1 ROTR B 2 Rd 1 ROTR W Rd 1 ROTR W 2 Rd 1 ROTR L ERd 1 ROTR L 2 ERd 1 ROTXL ROTXL B Rd 1 ROTXL B 2 Rd 1 ROTXL W Rd 1 ROTXL W 2 Rd 1 ROTXL L ERd 1 ROTXL L 2 ER...

Page 867: ... L ERd 1 ROTXR L 2 ERd 1 RTE RTE 2 2 3 3 1 RTS RTS 2 2 1 SHAL SHAL B Rd 1 SHAL B 2 Rd 1 SHAL W Rd 1 SHAL W 2 Rd 1 SHAL L ERd 1 SHAL L 2 ERd 1 SHAR SHAR B Rd 1 SHAR B 2 Rd 1 SHAR W Rd 1 SHAR W 2 Rd 1 SHAR L ERd 1 SHAR L 2 ERd 1 SHLL SHLL B Rd 1 SHLL B 2 Rd 1 SHLL W Rd 1 SHLL W 2 Rd 1 SHLL L ERd 1 SHLL L 2 ERd 1 SHLR SHLR B Rd 1 SHLR B 2 Rd 1 SHLR W Rd 1 SHLR W 2 Rd 1 SHLR L ERd 1 SHLR L 2 ERd 1 SLE...

Page 868: ... CCR d 32 ERd 5 1 STC W EXR d 32 ERd 5 1 STC W CCR ERd 2 1 1 STC W EXR ERd 2 1 1 STC W CCR aa 16 3 1 STC W EXR aa 16 3 1 STC W CCR aa 32 4 1 STC W EXR aa 32 4 1 STM STM L ERn ERn 1 SP 2 4 1 STM L ERn ERn 2 SP 2 6 1 STM L ERn ERn 3 SP 2 8 1 STMAC STMAC MACH ERd 1 1 STMAC MACL ERd 1 1 SUB SUB B Rs Rd 1 SUB W xx 16 Rd 2 SUB W Rs Rd 1 SUB L xx 32 ERd 3 SUB L ERs ERd 1 SUBS SUBS 1 2 4 ERd 1 SUBX SUBX x...

Page 869: ...XOR W xx 16 Rd 2 XOR W Rs Rd 1 XOR L xx 32 ERd 3 XOR L ERs ERd 2 XORC XORC xx 8 CCR 1 XORC xx 8 EXR 2 Notes 1 An internal operation may require between 0 and 3 additional states depending on the preceding instruction 2 When n bytes of data are transferred 3 2 when EXR is invalid 3 when EXR is valid 4 Only register ER0 ER1 ER4 or ER5 should be used when using the TAS instruction ...

Page 870: ... of execution Read effective address word size read No read or write Read 2nd word of current instruction word size read Legend R B Byte size read R W Word size read W B Byte size write W W Word size write M Transfer of the bus is not performed immediately after this cycle 2nd Address of 2nd word 3rd and 4th bytes 3rd Address of 3rd word 5th and 6th bytes 4th Address of 4th word 7th and 8th bytes ...

Page 871: ...ree state access with no wait states ø Address bus RD HWR LWR R W 2nd Fetching 2nd byte of instruction at jump address Fetching 1nd byte of instruction at jump address Fetching 4th byte of instruction Fetching 3rd byte of instruction R W EA High level Internal operation Figure A 1 Address Bus RD HWR and LWR Timing 8 Bit Bus Three State Access No Wait States ...

Page 872: ...NEXT BAND xx 3 Rd R W NEXT BAND xx 3 ERd R W 2nd R B EA R W M NEXT BAND xx 3 aa 8 R W 2nd R B EA R W M NEXT BAND xx 3 aa 16 R W 2nd R W 3rd R B EA R W M NEXT BAND xx 3 aa 32 R W 2nd R W 3rd R W 4th R B EA R W M NEXT BRA d 8 BT d 8 R W NEXT R W EA BRN d 8 BF d 8 R W NEXT R W EA BHI d 8 R W NEXT R W EA BLS d 8 R W NEXT R W EA BCC d 8 BHS d 8 R W NEXT R W EA BCS d 8 BLO d 8 R W NEXT R W EA BNE d 8 R ...

Page 873: ... 2nd Internal operation R W EA 1 state BVC d 16 R W 2nd Internal operation R W EA 1 state BVS d 16 R W 2nd Internal operation R W EA 1 state BPL d 16 R W 2nd Internal operation R W EA 1 state BMI d 16 R W 2nd Internal operation R W EA 1 state BGE d 16 R W 2nd Internal operation R W EA 1 state BLT d 16 R W 2nd Internal operation R W EA 1 state BGT d 16 R W 2nd Internal operation R W EA 1 state BLE ...

Page 874: ... EA R W M NEXT BIOR xx 3 Rd R W NEXT BIOR xx 3 ERd R W 2nd R B EA R W M NEXT BIOR xx 3 aa 8 R W 2nd R B EA R W M NEXT BIOR xx 3 aa 16 R W 2nd R W 3rd R B EA R W M NEXT BIOR xx 3 aa 32 R W 2nd R W 3rd R W 4th R B EA R W M NEXT BIST xx 3 Rd R W NEXT BIST xx 3 ERd R W 2nd R B M EA R W M NEXT W B EA BIST xx 3 aa 8 R W 2nd R B M EA R W M NEXT W B EA BIST xx 3 aa 16 R W 2nd R W 3rd R B M EA R W M NEXT W...

Page 875: ...SET xx 3 ERd R W 2nd R B M EA R W M NEXT W B EA BSET xx 3 aa 8 R W 2nd R B M EA R W M NEXT W B EA BSET xx 3 aa 16 R W 2nd R W 3rd R B M EA R W M NEXT W B EA BSET xx 3 aa 32 R W 2nd R W 3rd R W 4th R B M EA R W M NEXT W B EA BSET Rn Rd R W NEXT BSET Rn ERd R W 2nd R B M EA R W M NEXT W B EA BSET Rn aa 8 R W 2nd R B M EA R W M NEXT W B EA BSET Rn aa 16 R W 2nd R W 3rd R B M EA R W M NEXT W B EA BSET...

Page 876: ...A R W M NEXT CLRMAC R W NEXT Internal operation 1 state CMP B xx 8 Rd R W NEXT CMP B Rs Rd R W NEXT CMP W xx 16 Rd R W 2nd R W NEXT CMP W Rs Rd R W NEXT CMP L xx 32 ERd R W 2nd R W 3rd R W NEXT CMP L ERs ERd R W NEXT DAA Rd R W NEXT DAS Rd R W NEXT DEC B Rd R W NEXT DEC W 1 2 Rd R W NEXT DEC L 1 2 ERd R W NEXT DIVXS B Rs Rd R W 2nd R W NEXT Internal operation 11 states DIVXS W Rs ERd R W 2nd R W N...

Page 877: ...R W 3rd R W NEXT R W EA LDC d 32 ERs CCR R W 2nd R W 3rd R W 4th R W 5th R W NEXT R W EA LDC d 32 ERs EXR R W 2nd R W 3rd R W 4th R W 5th R W NEXT R W EA LDC ERs CCR R W 2nd R W NEXT Internal operation R W EA 1 state LDC ERs EXR R W 2nd R W NEXT Internal operation R W EA 1 state LDC aa 16 CCR R W 2nd R W 3rd R W NEXT R W EA LDC aa 16 EXR R W 2nd R W 3rd R W NEXT R W EA LDC aa 32 CCR R W 2nd R W 3r...

Page 878: ...A MOV B Rs ERd R W NEXT Internal operation W B EA 1 state MOV B Rs aa 8 R W NEXT W B EA MOV B Rs aa 16 R W 2nd R W NEXT W B EA MOV B Rs aa 32 R W 2nd R W 3rd R W NEXT W B EA MOV W xx 16 Rd R W 2nd R W NEXT MOV W Rs Rd R W NEXT MOV W ERs Rd R W NEXT R W EA MOV W d 16 ERs Rd R W 2nd R W NEXT R W EA MOV W d 32 ERs Rd R W 2nd R W 3rd R W 4th R W NEXT R W EA MOV W ERs Rd R W NEXT Internal operation R W...

Page 879: ...th R W 5th R W NEXT W W M EA W W EA 2 MOV L ERs ERd R W 2nd R W M NEXT Internal operation W W M EA W W EA 2 1 state MOV L ERs aa 16 R W 2nd R W M 3rd R W NEXT W W M EA W W EA 2 MOV L ERs aa 32 R W 2nd R W M 3rd R W 4th R W NEXT W W M EA W W EA 2 MOVFPE aa 16 Rd Cannot be used in this LSI MOVTPE Rs aa 16 MULXS B Rs Rd R W 2nd R W NEXT Internal operation 2 states MULXS W Rs ERd R W 2nd R W NEXT Inte...

Page 880: ...Rd R W NEXT ROTR B Rd R W NEXT ROTR B 2 Rd R W NEXT ROTR W Rd R W NEXT ROTR W 2 Rd R W NEXT ROTR L ERd R W NEXT ROTR L 2 ERd R W NEXT ROTXL B Rd R W NEXT ROTXL B 2 Rd R W NEXT ROTXL W Rd R W NEXT ROTXL W 2 Rd R W NEXT ROTXL L ERd R W NEXT ROTXL L 2 ERd R W NEXT ROTXR B Rd R W NEXT ROTXR B 2 Rd R W NEXT ROTXR W Rd R W NEXT ROTXR W 2 Rd R W NEXT ROTXR L ERd R W NEXT ROTXR L 2 ERd R W NEXT RTE R W NE...

Page 881: ... L ERd R W NEXT SHLR L 2 ERd R W NEXT SLEEP R W NEXT Internal operation M STC CCR Rd R W NEXT STC EXR Rd R W NEXT STC CCR ERd R W 2nd R W NEXT W W EA STC EXR ERd R W 2nd R W NEXT W W EA STC CCR d 16 ERd R W 2nd R W 3rd R W NEXT W W EA STC EXR d 16 ERd R W 2nd R W 3rd R W NEXT W W EA STC CCR d 32 ERd R W 2nd R W 3rd R W 4th R W 5th R W NEXT W W EA STC EXR d 32 ERd R W 2nd R W 3rd R W 4th R W 5th R ...

Page 882: ...MACL ERd R W NEXT SUB B Rs Rd R W NEXT SUB W xx 16 Rd R W 2nd R W NEXT SUB W Rs Rd R W NEXT SUB L xx 32 ERd R W 2nd R W 3rd R W NEXT SUB L ERs ERd R W NEXT SUBS 1 2 4 ERd R W NEXT SUBX xx 8 Rd R W NEXT SUBX Rs Rd R W NEXT TAS ERd 8 R W 2nd R W NEXT R B M EA W B EA TRAPA x 2 R W NEXT Internal operation W W stack L W W stack H W W stack EXR R W M VEC R W VEC 2 Internal operation R W 7 1 state 1 stat...

Page 883: ...ution of the instruction n is the initial value of R4L or R4 If n 0 these bus cycles are not executed 3 Repeated two times to save or restore two registers three times for three registers or four times for four registers 4 Start address after return 5 Start address of the program 6 Prefetch address equal to two plus the PC value pushed onto the stack In recovery from sleep mode or software standby...

Page 884: ...ds 7 for byte operands Si Di Ri Dn 0 1 Z C The i th bit of the source operand The i th bit of the destination operand The i th bit of the result The specified bit in the destination operand Not affected Modified according to the result of the instruction see definition Always cleared to 0 Always set to 1 Undetermined no guaranteed value Z flag before instruction execution C flag before instruction...

Page 885: ...m Rm ADDS ADDX H Sm 4 Dm 4 Dm 4 Rm 4 Sm 4 Rm 4 N Rm Z Z Rm R0 V Sm Dm Rm Sm Dm Rm C Sm Dm Dm Rm Sm Rm AND 0 N Rm Z Rm Rm 1 R0 ANDC Stores the corresponding bits of the result No flags change when the operand is EXR BAND C C Dn Bcc BCLR BIAND C C Dn BILD C Dn BIOR C C Dn BIST BIXOR C C Dn C Dn BLD C Dn BNOT BOR C C Dn BSET BSR BST BTST Z Dn BXOR C C Dn C Dn CLRMAC ...

Page 886: ... decimal arithmetic carry DAS N Rm Z Rm Rm 1 R0 C decimal arithmetic borrow DEC N Rm Z Rm Rm 1 R0 V Dm Rm DIVXS N Sm Dm Sm Dm Z Sm Sm 1 S0 DIVXU N Sm Z Sm Sm 1 S0 EEPMOV EXTS 0 N Rm Z Rm Rm 1 R0 EXTU 0 0 Z Rm Rm 1 R0 INC N Rm Z Rm Rm 1 R0 V Dm Rm JMP JSR LDC Stores the corresponding bits of the result No flags change when the operand is EXR LDM LDMAC MAC ...

Page 887: ... 4 N Rm Z Rm Rm 1 R0 V Dm Rm C Dm Rm NOP NOT 0 N Rm Z Rm Rm 1 R0 OR 0 N Rm Z Rm Rm 1 R0 ORC Stores the corresponding bits of the result No flags change when the operand is EXR POP 0 N Rm Z Rm Rm 1 R0 PUSH 0 N Rm Z Rm Rm 1 R0 ROTL 0 N Rm Z Rm Rm 1 R0 C Dm 1 bit shift or C Dm 1 2 bit shift ROTR 0 N Rm Z Rm Rm 1 R0 C D0 1 bit shift or C D1 2 bit shift ...

Page 888: ...shift V Dm Dm 1 Dm 2 Dm Dm 1 Dm 2 2 bit shift C Dm 1 bit shift or C Dm 1 2 bit shift SHAR 0 N Rm Z Rm Rm 1 R0 C D0 1 bit shift or C D1 2 bit shift SHLL 0 N Rm Z Rm Rm 1 R0 C Dm 1 bit shift or C Dm 1 2 bit shift SHLR 0 0 N Rm Z Rm Rm 1 R0 C D0 1 bit shift or C D1 2 bit shift SLEEP STC STM STMAC N 1 if MAC instruction resulted in negative value in MAC register Z 1 if MAC instruction resulted in zero...

Page 889: ...m 1 R0 V Sm Dm Rm Sm Dm Rm C Sm Dm Dm Rm Sm Rm SUBS SUBX H Sm 4 Dm 4 Dm 4 Rm 4 Sm 4 Rm 4 N Rm Z Z Rm R0 V Sm Dm Rm Sm Dm Rm C Sm Dm Dm Rm Sm Rm TAS 0 N Dm Z Dm Dm 1 D0 TRAPA XOR 0 N Rm Z Rm Rm 1 R0 XORC Stores the corresponding bits of the result No flags change when the operand is EXR ...

Page 890: ...4 TXPR3 TXPR2 TXPR1 H F807 TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8 H F808 TXCR TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 H F809 TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8 H F80A TXACK TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1 H F80B TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8 H F80C ABACK ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1 H F80D ABAC...

Page 891: ... STD_ID0 RTR IDE EXD_ID17 EXD_ID16 H F825 MC0 6 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H F826 MC0 7 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 H F827 MC0 8 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H F828 MC1 1 DLC3 DLC2 DLC1 DLC0 H F829 MC1 2 H F82A MC1 3 H F82B MC1 4 H F82C MC1 5 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 E...

Page 892: ...C0 H F849 MC5 2 H F84A MC5 3 H F84B MC5 4 H F84C MC5 5 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 H F84D MC5 6 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H F84E MC5 7 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 H F84F MC5 8 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H F850 MC6 1 DLC3 DLC2 DLC1 DLC0 H F851 MC6 2 H F852 MC6 ...

Page 893: ...C10 2 H F872 MC10 3 H F873 MC10 4 H F874 MC10 5 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 H F875 MC10 6 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H F876 MC10 7 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 H F877 MC10 8 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H F878 MC11 1 DLC3 DLC2 DLC1 DLC0 H F879 MC11 2 H F87A MC11 3...

Page 894: ...XD_ID1 EXD_ID0 H F897 MC14 8 EXD_ID15 EXD_ID14 EXD_ID13 EXD_ID12 EXD_ID11 EXD_ID10 EXD_ID9 EXD_ID8 H F898 MC15 1 DLC3 DLC2 DLC1 DLC0 H F899 MC15 2 H F89A MC15 3 H F89B MC15 4 H F89C MC15 5 STD_ID2 STD_ID1 STD_ID0 RTR IDE EXD_ID17 EXD_ID16 H F89D MC15 6 STD_ID10 STD_ID9 STD_ID8 STD_ID7 STD_ID6 STD_ID5 STD_ID4 STD_ID3 H F89E MC15 7 EXD_ID7 EXD_ID6 EXD_ID5 EXD_ID4 EXD_ID3 EXD_ID2 EXD_ID1 EXD_ID0 H F8...

Page 895: ...s H F8CF MD3 8 MSG_DATA_8 8 bits H F8D0 MD4 1 MSG_DATA_1 8 bits H F8D1 MD4 2 MSG_DATA_2 8 bits H F8D2 MD4 3 MSG_DATA_3 8 bits H F8D3 MD4 4 MSG_DATA_4 8 bits H F8D4 MD4 5 MSG_DATA_5 8 bits H F8D5 MD4 6 MSG_DATA_6 8 bits H F8D6 MD4 7 MSG_DATA_7 8 bits H F8D7 MD4 8 MSG_DATA_8 8 bits H F8D8 MD5 1 MSG_DATA_1 8 bits H F8D9 MD5 2 MSG_DATA_2 8 bits H F8DA MD5 3 MSG_DATA_3 8 bits H F8DB MD5 4 MSG_DATA_4 8 ...

Page 896: ... MD8 8 MSG_DATA_8 8 bits H F8F8 MD9 1 MSG_DATA_1 8 bits H F8F9 MD9 2 MSG_DATA_2 8 bits H F8FA MD9 3 MSG_DATA_3 8 bits H F8FB MD9 4 MSG_DATA_4 8 bits H F8FC MD9 5 MSG_DATA_5 8 bits H F8FD MD9 6 MSG_DATA_6 8 bits H F8FE MD9 7 MSG_DATA_7 8 bits H F8FF MD9 8 MSG_DATA_8 8 bits H F900 MD10 1 MSG_DATA_1 8 bits H F901 MD10 2 MSG_DATA_2 8 bits H F902 MD10 3 MSG_DATA_3 8 bits H F903 MD10 4 MSG_DATA_4 8 bits...

Page 897: ...91B MD13 4 MSG_DATA_4 8 bits H F91C MD13 5 MSG_DATA_5 8 bits H F91D MD13 6 MSG_DATA_6 8 bits H F91E MD13 7 MSG_DATA_7 8 bits H F91F MD13 8 MSG_DATA_8 8 bits H F920 MD14 1 MSG_DATA_1 8 bits H F921 MD14 2 MSG_DATA_2 8 bits H F922 MD14 3 MSG_DATA_3 8 bits H F923 MD14 4 MSG_DATA_4 8 bits H F924 MD14 5 MSG_DATA_5 8 bits H F925 MD14 6 MSG_DATA_6 8 bits H F926 MD14 7 MSG_DATA_7 8 bits H F927 MD14 8 MSG_D...

Page 898: ...l 8 H FC12 PWOCR2 OE2H OE2G OE2F OE2E OE2D OE2C OE2B OE2A PWM timer 2 H FC14 PWPR2 OPS2H OPS2G OPS2F OPS2E OPS2D OPS2C OPS2B OPS2A H FC16 PWCYR2 16 H FC18 PWBFR2A TDS DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 H FC1A PWBFR2B TDS DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 H FC1C PWBFR2C TDS DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 H FC1E PWBFR2D TDS DT9 DT8 DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0 H FC20 PHDDR PH7...

Page 899: ...PCRB MSTPB7 MSTPB6 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 H FDEA MSTPCRC MSTPC7 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 H FDEB PFCR AE3 AE2 AE1 AE0 H FDEC LPWRCR DTON LSON NESEL SUBSTP RFCUT STC1 STC0 H FE00 BARA PBC 32 H FE01 BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 H FE02 BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 H FE03 BAA7 BAA6 BAA5 BAA4 BAA3 BAA2 BAA1 BAA0 H FE04 BARB H FE05 BAA23 BA...

Page 900: ...DR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 H FE2E NDRH NDR11 NDR10 NDR9 NDR8 H FE2F NDRL NDR3 NDR2 NDR1 NDR0 H FE30 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR PORT 8 H FE30 P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR H FE32 P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR H FE34 P5DDR P52DDR P51DDR P50DDR H FE39 PADDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR...

Page 901: ...E8E TGR3D H FE8F H FE90 TCR4 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU4 8 16 H FE91 TMDR4 MD3 MD2 MD1 MD0 H FE92 TIOR4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H FE94 TIER4 TTGE TCIEU TCIEV TGIEB TGIEA H FE95 TSR4 TCFD TCFU TCFV TGFB TGFA H FE96 TCNT4 H FE97 H FE98 TGR4A H FE99 H FE9A TGR4B H FE9B H FEA0 TCR5 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU5 8 16 H FEA1 TMDR5 MD3 MD2 MD1 MD0 H FEA...

Page 902: ...ntroller 8 H FED1 ASTCR AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 H FED2 WCRH W71 W70 W61 W60 W51 W50 W41 W40 H FED3 WCRL W31 W30 W21 W20 W11 W10 W01 W00 H FED4 BCRH ICIS1 ICIS0 BRSTRM BRSTS1 BRSTS0 H FED5 BCRL WDBE WAITE H FEDB RAMER RAMS RAM2 RAM1 RAM0 ROM 8 H FF00 P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR PORT 8 H FF01 P2DR P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR H FF02 P3DR P3...

Page 903: ...H FF19 H FF1A TGR0B H FF1B H FF1C TGR0C H FF1D H FF1E TGR0D H FF1F H FF20 TCR1 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU1 8 16 H FF21 TMDR1 MD3 MD2 MD1 MD0 H FF22 TIOR1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H FF24 TIER1 TTGE TCIEU TCIEV TGIEB TGIEA H FF25 TSR1 TCFD TCFU TCFV TGFB TGFA H FF26 TNCT1 H FF27 H FF28 TGR1A H FF29 H FF2A TGR1B H FF2B H FF30 TCR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 ...

Page 904: ...CKS0 H FF79 BRR0 H FF7A SCR0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 H FF7B TDR0 H FF7C SSR0 TDRE RDRF ORER FER PER TEND MPB MPBT SSR0 TDRE RDRF ORER ERS PER TEND MPB MPBT H FF7D RDR0 H FF7E SCMR0 SDIR SINV SMIF H FF80 SMR1 C A CHR PE O E STOP MP CKS1 CKS0 SCI1 smart card interface 1 8 SMR1 GM BLK PE O E BCP1 BCP0 CKS1 CKS0 H FF81 BRR1 H FF82 SCR1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 H FF83 TDR1 H FF84 SSR...

Page 905: ... CH2 CH1 CH0 H FF99 ADCR TRGS1 TRGS0 CKS1 CKS0 H FFA2 read write TCSR1 OVF WT IT TME PSS RST NMI CKS2 CKS1 CKS0 WDT1 8 H FFA3 read TCNT1 H FFA8 FLMCR1 FWE SWE ESU PSU EV PV E P ROM 8 H FFA9 FLMCR2 FLER H FFAA EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 H FFAB EBR2 EB9 EB8 H FFAC FLPWCR PDWND H FFB0 PORT1 P17 P16 P15 P14 P13 P12 P11 P10 PORT 8 H FFB1 PORT2 P27 P26 P25 P24 P23 P22 P21 P20 H FFB2 PORT3 P37 ...

Page 906: ... 0 R W 5 DAE 0 R W 4 1 3 1 0 1 2 1 1 1 D A Enabled DAOE1 0 1 Conversion result DAE 0 1 0 1 DAOE0 0 1 0 1 Channel 0 and 1 D A conversion disabled Channel 0 D A conversion enabled Channel 1 D A conversion disabled Channel 0 and 1 D A conversion enabled Channel 0 D A conversion disabled Channel 1 D A conversion enabled Channel 0 and 1 D A conversion enabled Channel 0 and 1 D A conversion enabled D A ...

Page 907: ...ination side is repeat area or block area 1 Source side is repeat area or block area DTC Mode 0 Normal mode Repeat mode 0 1 1 Block transfer mode 0 1 Destination Address Mode 0 DAR is fixed DAR is incremented after a transfer by 1 when Sz 0 by 2 when Sz 1 0 1 DAR is decremented after a transfer by 1 when Sz 0 by 2 when Sz 1 1 Source Address Mode 0 SAR is fixed SAR is incremented after a transfer b...

Page 908: ...Enable 0 End of DTC data transfer 1 DTC chain transfer SAR DTC Source Address Register H EBC0 H EFBF DTC 23 Unde fined Bit Initial value Read Write 22 Unde fined 21 Unde fined 20 Unde fined 19 Unde fined 4 Unde fined 3 Unde fined 2 Unde fined 1 Unde fined 0 Unde fined Specify DTC transfer data source address DAR DTC Destination Address Register H EBC0 H EFBF DTC 23 Unde fined Bit Initial value Rea...

Page 909: ...d 3 Unde fined 2 Unde fined 1 Unde fined 0 Unde fined CRAH CRAL Specify the number of DTC data transfers CRB DTC Transfer Count Register B H EBC0 H EFBF DTC 15 Unde fined Bit Initial value Read Write 14 Unde fined 13 Unde fined 12 Unde fined 11 Unde fined 10 Unde fined 9 Unde fined 8 Unde fined 7 Unde fined 6 Unde fined 5 Unde fined 4 Unde fined 3 Unde fined 2 Unde fined 1 Unde fined 0 Unde fined ...

Page 910: ...iority TXPR1 TXPR15 Halt Request HCAN normal operating mode HCAN halt mode transition request HCAN Sleep Mode Release 0 HCAN sleep mode release by CAN bus operation disabled 1 HCAN sleep mode release by CAN bus operation enabled 7 MCR7 0 R W 6 0 5 MCR5 0 R W 4 0 3 0 0 MCR0 1 R W 2 MCR2 0 R W 1 MCR1 0 R W Bit Initial value Read Write Reset Request 0 Normal operating mode MCR0 0 and GSR3 0 Setting c...

Page 911: ...EC 96 and REC 96 or TEC 256 1 When TEC 96 or REC 96 Bus Off Flag 0 Reset condition Recovery from bus off state 1 When TEC 256 bus off state Reset Status Bit 0 Normal operating state Setting condition After an HCAN internal reset 1 Configuration mode Reset condition MCR0 reset mode and sleep mode Message Transmission Status Flag 0 Message transmission period 1 Reset condition Idle period ...

Page 912: ...1 0 0 1 1 0 1 0 1 7 BCR15 0 R W 6 BCR14 0 R W 5 BCR13 0 R W 4 BCR12 0 R W 3 BCR11 0 R W 0 BCR8 0 R W 2 BCR10 0 R W 1 BCR9 0 R W Bit Initial value Read Write Time Segment 2 0 Setting prohibited TSEG2 2 time quanta 0 1 TSEG2 3 time quanta 0 TSEG2 4 time quanta 1 0 1 1 TSEG2 5 time quanta TSEG2 6 time quanta 0 1 TSEG2 7 time quanta 0 TSEG2 8 time quanta 1 0 1 Time Segment 1 0 Setting prohibited Setti...

Page 913: ...ion 1 Corresponding mailbox is set for reception TXPR Transmit Wait Register H F806 HCAN 15 TXPR7 0 R W 14 TXPR6 0 R W 13 TXPR5 0 R W 12 TXPR4 0 R W 11 TXPR3 0 R W 8 0 10 TXPR2 0 R W 9 TXPR1 0 R W 7 TXPR15 0 R W 6 TXPR14 0 R W 5 TXPR13 0 R W 4 TXPR12 0 R W 3 TXPR11 0 R W 0 TXPR8 0 R W 2 TXPR10 0 R W 1 TXPR9 0 R W Bit Initial value Read Write Bit Initial value Read Write Transmit Wait Register 0 Tr...

Page 914: ...mpletion of TXPR clearing when transmit message is canceled normally 1 TXPR cleared for corresponding mailbox transmit message cancellation TXACK Transmit Acknowledge Register H F80A HCAN 15 TXACK7 0 R W 14 TXACK6 0 R W 13 TXACK5 0 R W 12 TXACK4 0 R W 11 TXACK3 0 R W 8 0 10 TXACK2 0 R W 9 TXACK1 0 R W 7 TXACK15 0 R W 6 TXACK14 0 R W 5 TXACK13 0 R W 4 TXACK12 0 R W 3 TXACK11 0 R W 0 TXACK8 0 R W 2 ...

Page 915: ...ransmit message cancellation for corresponding mailbox Note Only 1 can be written to clear the flag RXPR Receive Complete Register H F80E HCAN 15 RXPR7 0 R W 14 RXPR6 0 R W 13 RXPR5 0 R W 12 RXPR4 0 R W 11 RXPR3 0 R W 8 RXPR0 0 R W 10 RXPR2 0 R W 9 RXPR1 0 R W 7 RXPR15 0 R W 6 RXPR14 0 R W 5 RXPR13 0 R W 4 RXPR12 0 R W 3 RXPR11 0 R W 0 RXPR8 0 R W 2 RXPR10 0 R W 1 RXPR9 0 R W Bit Initial value Rea...

Page 916: ... RFPR1 0 R W 7 RFPR15 0 R W 6 RFPR14 0 R W 5 RFPR13 0 R W 4 RFPR12 0 R W 3 RFPR11 0 R W 0 RFPR8 0 R W 2 RFPR10 0 R W 1 RFPR9 0 R W Bit Initial value Read Write Bit Initial value Read Write Remote Request Register 0 Clearing condition Writing 1 1 Completion of remote frame reception in corresponding mailbox Note Only 1 can be written to clear the flag ...

Page 917: ...es the receive interrupt requests in MBIMR 1 Remote frame received and stored in mailbox Setting conditions When remote frame reception is completed when corresponding MBIMR 0 0 Clearing condition Writing 1 1 Error warning state caused by transmit error Setting condition When TEC 96 Transmit Overload Warning Interrupt Flag 0 Clearing condition Writing 1 1 Error warning state caused by receive erro...

Page 918: ...red by completion of transmission or completion of transmission abort Unread Interrupt Flag Clearing condition Clearing of all bits in UMSR unread message status register Unread message overwrite Setting condition When UMSR unread message status register is set 0 1 CAN bus idle state Clearing condition Writing 1 CAN bus operation in HCAN sleep mode Setting condition Bus operation dominant bit dete...

Page 919: ...IMR1 1 R W 7 MBIMR15 1 R W 6 MBIMR14 1 R W 5 MBIMR13 1 R W 4 MBIMR12 1 R W 3 MBIMR11 1 R W 0 MBIMR8 1 R W 2 MBIMR10 1 R W 1 MBIMR9 1 R W Bit Initial value Read Write Bit Initial value Read Write Mailbox Interrupt Mask 0 Transmitting Interrupt request to CPU due to TXPR clearing Receiving Interrupt request to CPU due to RXPR setting 1 Interrupt requests to CPU disabled ...

Page 920: ...e interrupt request to CPU by IRR5 enabled 1 Error passive interrupt request to CPU by IRR5 disabled Receive Overload Warning Interrupt Mask 0 REC error warning interrupt request to CPU by IRR4 enabled 1 REC error warning interrupt request to CPU by IRR4 disabled Transmit Overload Warning Interrupt Mask 0 TEC error warning interrupt request to CPU by IRR3 enabled 1 TEC error warning interrupt requ...

Page 921: ... enabled 1 Mailbox empty interrupt request to CPU by IRR8 disabled Unread Interrupt Mask 0 Unread message overwrite interrupt request to CPU by IRR9 enabled 1 Unread message overwrite interrupt request to CPU by IRR9 disabled Bus Operation Interrupt Mask 0 Bus operation interrupt request to CPU by IRR12 enabled 1 Bus operation interrupt request to CPU by IRR12 disabled ...

Page 922: ...R W 13 UMSR5 0 R W 12 UMSR4 0 R W 11 UMSR3 0 R W 8 UMSR0 0 R W 10 UMSR2 0 R W 9 UMSR1 0 R W 7 UMSR15 0 R W 6 UMSR14 0 R W 5 UMSR13 0 R W 4 UMSR12 0 R W 3 UMSR11 0 R W 0 UMSR8 0 R W 2 UMSR10 0 R W 1 UMSR9 0 R W Bit Initial value Read Write Bit Initial value Read Write Note Only 1 can be written to clear the flag Unread Message Status Flags 0 Clearing condition Writing 1 x 15 to 0 1 Unread receive m...

Page 923: ... W 3 LAFMH11 0 R W 0 LAFMH8 0 R W 2 LAFMH10 0 R W 1 LAFMH9 0 R W Bit Initial value Read Write LAFMH Bit Initial value Read Write LAFMH Bits 7 to 0 and 15 to 13 11 Bit Identifier Filter 0 Stored in RX0 receive only mailbox depending on bit match between RX0 message identifier and receive message identifier Care 1 Stored in RX0 receive only mailbox regardless of bit match between RX0 message identif...

Page 924: ...l value Read Write MC01 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC02 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC03 Data Length Code 0 Data length 0 byte Data length 1 ...

Page 925: ...ndefined R W Bit Initial value Read Write MC06 Standard Identifier Set the identifier standard identifier of data frames and remote frames Extended Identifier Set the identifier extended identifier of data frames and remote frames Remote Transmission Request 0 Data frame 1 Remote frame Identifier Extension 0 Standard format 1 Extended format Standard Identifier Set the identifier standard identifi...

Page 926: ...ad Write MC08 Extended Identifier Set the identifier extended identifier of data frames and remote frames 7 EXD_ID7 Undefined R W 6 EXD_ID6 Undefined R W 5 EXD_ID5 Undefined R W 4 EXD_ID4 Undefined R W 3 EXD_ID3 Undefined R W 0 EXD_ID0 Undefined R W 2 EXD_ID2 Undefined R W 1 EXD_ID1 Undefined R W Bit Initial value Read Write MC07 Extended Identifier Set the identifier extended identifier of data f...

Page 927: ...l value Read Write MC11 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC12 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC13 Data Length Code 0 Data length 0 byte Data length 1 ...

Page 928: ...ndefined R W Bit Initial value Read Write MC16 Standard Identifier Set the identifier standard identifier of data frames and remote frames Extended Identifier Set the identifier extended identifier of data frames and remote frames Remote Transmission Request 0 Data frame 1 Remote frame Identifier Extension 0 Standard format 1 Extended format Standard Identifier Set the identifier standard identifi...

Page 929: ...ad Write MC18 Extended Identifier Set the identifier extended identifier of data frames and remote frames Bit Initial value Read Write MC17 Extended Identifier Set the identifier extended identifier of data frames and remote frames 7 EXD_ID7 Undefined R W 6 EXD_ID6 Undefined R W 5 EXD_ID5 Undefined R W 4 EXD_ID4 Undefined R W 3 EXD_ID3 Undefined R W 0 EXD_ID0 Undefined R W 2 EXD_ID2 Undefined R W ...

Page 930: ...l value Read Write MC21 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC22 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC23 Data Length Code 0 Data length 0 byte Data length 1 ...

Page 931: ...ndefined R W Bit Initial value Read Write MC26 Standard Identifier Set the identifier standard identifier of data frames and remote frames Extended Identifier Set the identifier extended identifier of data frames and remote frames Remote Transmission Request 0 Data frame 1 Remote frame Identifier Extension 0 Standard format 1 Extended format Standard Identifier Set the identifier standard identifi...

Page 932: ...ad Write MC28 Extended Identifier Set the identifier extended identifier of data frames and remote frames Bit Initial value Read Write MC27 Extended Identifier Set the identifier extended identifier of data frames and remote frames 7 EXD_ID7 Undefined R W 6 EXD_ID6 Undefined R W 5 EXD_ID5 Undefined R W 4 EXD_ID4 Undefined R W 3 EXD_ID3 Undefined R W 0 EXD_ID0 Undefined R W 2 EXD_ID2 Undefined R W ...

Page 933: ...l value Read Write MC31 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC32 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC33 Data Length Code 0 Data length 0 byte Data length 1 ...

Page 934: ...ndefined R W Bit Initial value Read Write MC36 Standard Identifier Set the identifier standard identifier of data frames and remote frames Extended Identifier Set the identifier extended identifier of data frames and remote frames Remote Transmission Request 0 Data frame 1 Remote frame Identifier Extension 0 Standard format 1 Extended format Standard Identifier Set the identifier standard identifi...

Page 935: ...ad Write MC38 Extended Identifier Set the identifier extended identifier of data frames and remote frames Bit Initial value Read Write MC37 Extended Identifier Set the identifier extended identifier of data frames and remote frames 7 EXD_ID7 Undefined R W 6 EXD_ID6 Undefined R W 5 EXD_ID5 Undefined R W 4 EXD_ID4 Undefined R W 3 EXD_ID3 Undefined R W 0 EXD_ID0 Undefined R W 2 EXD_ID2 Undefined R W ...

Page 936: ...l value Read Write MC41 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC42 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC43 Data Length Code 0 Data length 0 byte Data length 1 ...

Page 937: ...ndefined R W Bit Initial value Read Write MC46 Standard Identifier Set the identifier standard identifier of data frames and remote frames Extended Identifier Set the identifier extended identifier of data frames and remote frames Remote Transmission Request 0 Data frame 1 Remote frame Identifier Extension 0 Standard format 1 Extended format Standard Identifier Set the identifier standard identifi...

Page 938: ...ad Write MC48 Extended Identifier Set the identifier extended identifier of data frames and remote frames Bit Initial value Read Write MC47 Extended Identifier Set the identifier extended identifier of data frames and remote frames 7 EXD_ID7 Undefined R W 6 EXD_ID6 Undefined R W 5 EXD_ID5 Undefined R W 4 EXD_ID4 Undefined R W 3 EXD_ID3 Undefined R W 0 EXD_ID0 Undefined R W 2 EXD_ID2 Undefined R W ...

Page 939: ...l value Read Write MC51 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC52 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC53 Data Length Code 0 Data length 0 byte Data length 1 ...

Page 940: ...ndefined R W Bit Initial value Read Write MC56 Standard Identifier Set the identifier standard identifier of data frames and remote frames Extended Identifier Set the identifier extended identifier of data frames and remote frames Remote Transmission Request 0 Data frame 1 Remote frame Identifier Extension 0 Standard format 1 Extended format Standard Identifier Set the identifier standard identifi...

Page 941: ...ad Write MC58 Extended Identifier Set the identifier extended identifier of data frames and remote frames Bit Initial value Read Write MC57 Extended Identifier Set the identifier extended identifier of data frames and remote frames 7 EXD_ID7 Undefined R W 6 EXD_ID6 Undefined R W 5 EXD_ID5 Undefined R W 4 EXD_ID4 Undefined R W 3 EXD_ID3 Undefined R W 0 EXD_ID0 Undefined R W 2 EXD_ID2 Undefined R W ...

Page 942: ...l value Read Write MC61 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC62 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC63 Data Length Code 0 Data length 0 byte Data length 1 ...

Page 943: ...ndefined R W Bit Initial value Read Write MC66 Standard Identifier Set the identifier standard identifier of data frames and remote frames Extended Identifier Set the identifier extended identifier of data frames and remote frames Remote Transmission Request 0 Data frame 1 Remote frame Identifier Extension 0 Standard format 1 Extended format Standard Identifier Set the identifier standard identifi...

Page 944: ...ad Write MC68 Extended Identifier Set the identifier extended identifier of data frames and remote frames Bit Initial value Read Write MC67 Extended Identifier Set the identifier extended identifier of data frames and remote frames 7 EXD_ID7 Undefined R W 6 EXD_ID6 Undefined R W 5 EXD_ID5 Undefined R W 4 EXD_ID4 Undefined R W 3 EXD_ID3 Undefined R W 0 EXD_ID0 Undefined R W 2 EXD_ID2 Undefined R W ...

Page 945: ...l value Read Write MC71 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC72 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC73 Data Length Code 0 Data length 0 byte Data length 1 ...

Page 946: ...ndefined R W Bit Initial value Read Write MC76 Standard Identifier Set the identifier standard identifier of data frames and remote frames Extended Identifier Set the identifier extended identifier of data frames and remote frames Remote Transmission Request 0 Data frame 1 Remote frame Identifier Extension 0 Standard format 1 Extended format Standard Identifier Set the identifier standard identifi...

Page 947: ...ad Write MC78 Extended Identifier Set the identifier extended identifier of data frames and remote frames Bit Initial value Read Write MC77 Extended Identifier Set the identifier extended identifier of data frames and remote frames 7 EXD_ID7 Undefined R W 6 EXD_ID6 Undefined R W 5 EXD_ID5 Undefined R W 4 EXD_ID4 Undefined R W 3 EXD_ID3 Undefined R W 0 EXD_ID0 Undefined R W 2 EXD_ID2 Undefined R W ...

Page 948: ...l value Read Write MC81 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC82 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC83 Data Length Code 0 Data length 0 byte Data length 1 ...

Page 949: ...ndefined R W Bit Initial value Read Write MC86 Standard Identifier Set the identifier standard identifier of data frames and remote frames Extended Identifier Set the identifier extended identifier of data frames and remote frames Remote Transmission Request 0 Data frame 1 Remote frame Identifier Extension 0 Standard format 1 Extended format Standard Identifier Set the identifier standard identifi...

Page 950: ...ad Write MC88 Extended Identifier Set the identifier extended identifier of data frames and remote frames Bit Initial value Read Write MC87 Extended Identifier Set the identifier extended identifier of data frames and remote frames 7 EXD_ID7 Undefined R W 6 EXD_ID6 Undefined R W 5 EXD_ID5 Undefined R W 4 EXD_ID4 Undefined R W 3 EXD_ID3 Undefined R W 0 EXD_ID0 Undefined R W 2 EXD_ID2 Undefined R W ...

Page 951: ...l value Read Write MC91 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC92 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC93 Data Length Code 0 Data length 0 byte Data length 1 ...

Page 952: ...ndefined R W Bit Initial value Read Write MC96 Standard Identifier Set the identifier standard identifier of data frames and remote frames Extended Identifier Set the identifier extended identifier of data frames and remote frames Remote Transmission Request 0 Data frame 1 Remote frame Identifier Extension 0 Standard format 1 Extended format Standard Identifier Set the identifier standard identifi...

Page 953: ...ad Write MC98 Extended Identifier Set the identifier extended identifier of data frames and remote frames Bit Initial value Read Write MC97 Extended Identifier Set the identifier extended identifier of data frames and remote frames 7 EXD_ID7 Undefined R W 6 EXD_ID6 Undefined R W 5 EXD_ID5 Undefined R W 4 EXD_ID4 Undefined R W 3 EXD_ID3 Undefined R W 0 EXD_ID0 Undefined R W 2 EXD_ID2 Undefined R W ...

Page 954: ...Initial value Read Write MC101 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC102 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC103 Data Length Code 0 Data length 0 byte Data ...

Page 955: ...ndefined R W Bit Initial value Read Write MC106 Standard Identifier Set the identifier standard identifier of data frames and remote frames Extended Identifier Set the identifier extended identifier of data frames and remote frames Remote Transmission Request 0 Data frame 1 Remote frame Identifier Extension 0 Standard format 1 Extended format Standard Identifier Set the identifier standard identif...

Page 956: ...d Write MC108 Extended Identifier Set the identifier extended identifier of data frames and remote frames Bit Initial value Read Write MC107 Extended Identifier Set the identifier extended identifier of data frames and remote frames 7 EXD_ID7 Undefined R W 6 EXD_ID6 Undefined R W 5 EXD_ID5 Undefined R W 4 EXD_ID4 Undefined R W 3 EXD_ID3 Undefined R W 0 EXD_ID0 Undefined R W 2 EXD_ID2 Undefined R W...

Page 957: ...Initial value Read Write MC111 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC112 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC113 Data Length Code 0 Data length 0 byte Data ...

Page 958: ...ndefined R W Bit Initial value Read Write MC116 Standard Identifier Set the identifier standard identifier of data frames and remote frames Extended Identifier Set the identifier extended identifier of data frames and remote frames Remote Transmission Request 0 Data frame 1 Remote frame Identifier Extension 0 Standard format 1 Extended format Standard Identifier Set the identifier standard identif...

Page 959: ...d Write MC118 Extended Identifier Set the identifier extended identifier of data frames and remote frames Bit Initial value Read Write MC117 Extended Identifier Set the identifier extended identifier of data frames and remote frames 7 EXD_ID7 Undefined R W 6 EXD_ID6 Undefined R W 5 EXD_ID5 Undefined R W 4 EXD_ID4 Undefined R W 3 EXD_ID3 Undefined R W 0 EXD_ID0 Undefined R W 2 EXD_ID2 Undefined R W...

Page 960: ...Initial value Read Write MC121 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC122 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC123 Data Length Code 0 Data length 0 byte Data ...

Page 961: ...ndefined R W Bit Initial value Read Write MC126 Standard Identifier Set the identifier standard identifier of data frames and remote frames Extended Identifier Set the identifier extended identifier of data frames and remote frames Remote Transmission Request 0 Data frame 1 Remote frame Identifier Extension 0 Standard format 1 Extended format Standard Identifier Set the identifier standard identif...

Page 962: ...d Write MC128 Extended Identifier Set the identifier extended identifier of data frames and remote frames Bit Initial value Read Write MC127 Extended Identifier Set the identifier extended identifier of data frames and remote frames 7 EXD_ID7 Undefined R W 6 EXD_ID6 Undefined R W 5 EXD_ID5 Undefined R W 4 EXD_ID4 Undefined R W 3 EXD_ID3 Undefined R W 0 EXD_ID0 Undefined R W 2 EXD_ID2 Undefined R W...

Page 963: ...Initial value Read Write MC131 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC132 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC133 Data Length Code 0 Data length 0 byte Data ...

Page 964: ...ndefined R W Bit Initial value Read Write MC136 Standard Identifier Set the identifier standard identifier of data frames and remote frames Extended Identifier Set the identifier extended identifier of data frames and remote frames Remote Transmission Request 0 Data frame 1 Remote frame Identifier Extension 0 Standard format 1 Extended format Standard Identifier Set the identifier standard identif...

Page 965: ...d Write MC138 Extended Identifier Set the identifier extended identifier of data frames and remote frames Bit Initial value Read Write MC137 Extended Identifier Set the identifier extended identifier of data frames and remote frames 7 EXD_ID7 Undefined R W 6 EXD_ID6 Undefined R W 5 EXD_ID5 Undefined R W 4 EXD_ID4 Undefined R W 3 EXD_ID3 Undefined R W 0 EXD_ID0 Undefined R W 2 EXD_ID2 Undefined R W...

Page 966: ...Initial value Read Write MC141 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC142 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC143 Data Length Code 0 Data length 0 byte Data ...

Page 967: ...ndefined R W Bit Initial value Read Write MC146 Standard Identifier Set the identifier standard identifier of data frames and remote frames Extended Identifier Set the identifier extended identifier of data frames and remote frames Remote Transmission Request 0 Data frame 1 Remote frame Identifier Extension 0 Standard format 1 Extended format Standard Identifier Set the identifier standard identif...

Page 968: ...d Write MC148 Extended Identifier Set the identifier extended identifier of data frames and remote frames Bit Initial value Read Write MC147 Extended Identifier Set the identifier extended identifier of data frames and remote frames 7 EXD_ID7 Undefined R W 6 EXD_ID6 Undefined R W 5 EXD_ID5 Undefined R W 4 EXD_ID4 Undefined R W 3 EXD_ID3 Undefined R W 0 EXD_ID0 Undefined R W 2 EXD_ID2 Undefined R W...

Page 969: ...Initial value Read Write MC151 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC152 7 Undefined R W 6 Undefined R W 5 Undefined R W 4 Undefined R W 3 Undefined R W 0 Undefined R W 2 Undefined R W 1 Undefined R W Bit Initial value Read Write MC153 Data Length Code 0 Data length 0 byte Data ...

Page 970: ...ndefined R W Bit Initial value Read Write MC156 Standard Identifier Set the identifier standard identifier of data frames and remote frames Extended Identifier Set the identifier extended identifier of data frames and remote frames Remote Transmission Request 0 Data frame 1 Remote frame Identifier Extension 0 Standard format 1 Extended format Standard Identifier Set the identifier standard identif...

Page 971: ...d Write MC158 Extended Identifier Set the identifier extended identifier of data frames and remote frames Bit Initial value Read Write MC157 Extended Identifier Set the identifier extended identifier of data frames and remote frames 7 EXD_ID7 Undefined R W 6 EXD_ID6 Undefined R W 5 EXD_ID5 Undefined R W 4 EXD_ID4 Undefined R W 3 EXD_ID3 Undefined R W 0 EXD_ID0 Undefined R W 2 EXD_ID2 Undefined R W...

Page 972: ...ATA_3 8 bits MSG_DATA_4 8 bits MSG_DATA_5 8 bits MSG_DATA_6 8 bits MSG_DATA_7 8 bits MSG_DATA_8 8 bits MD11 Message Data 11 H F8B8 HCAN MD12 Message Data 12 H F8B9 HCAN MD13 Message Data 13 H F8BA HCAN MD14 Message Data 14 H F8BB HCAN MD15 Message Data 15 H F8BC HCAN MD16 Message Data 16 H F8BD HCAN MD17 Message Data 17 H F8BE HCAN MD18 Message Data 18 H F8BF HCAN MD11 MD12 MD13 MD14 MD15 MD16 MD1...

Page 973: ...ATA_3 8 bits MSG_DATA_4 8 bits MSG_DATA_5 8 bits MSG_DATA_6 8 bits MSG_DATA_7 8 bits MSG_DATA_8 8 bits MD31 Message Data 31 H F8C8 HCAN MD32 Message Data 32 H F8C9 HCAN MD33 Message Data 33 H F8CA HCAN MD34 Message Data 34 H F8CB HCAN MD35 Message Data 35 H F8CC HCAN MD36 Message Data 36 H F8CD HCAN MD37 Message Data 37 H F8CE HCAN MD38 Message Data 38 H F8CF HCAN MD31 MD32 MD33 MD34 MD35 MD36 MD3...

Page 974: ...ATA_3 8 bits MSG_DATA_4 8 bits MSG_DATA_5 8 bits MSG_DATA_6 8 bits MSG_DATA_7 8 bits MSG_DATA_8 8 bits MD51 Message Data 51 H F8D8 HCAN MD52 Message Data 52 H F8D9 HCAN MD53 Message Data 53 H F8DA HCAN MD54 Message Data 54 H F8DB HCAN MD55 Message Data 55 H F8DC HCAN MD56 Message Data 56 H F8DD HCAN MD57 Message Data 57 H F8DE HCAN MD58 Message Data 58 H F8DF HCAN MD51 MD52 MD53 MD54 MD55 MD56 MD5...

Page 975: ...ATA_3 8 bits MSG_DATA_4 8 bits MSG_DATA_5 8 bits MSG_DATA_6 8 bits MSG_DATA_7 8 bits MSG_DATA_8 8 bits MD71 Message Data 71 H F8E8 HCAN MD72 Message Data 72 H F8E9 HCAN MD73 Message Data 73 H F8EA HCAN MD74 Message Data 74 H F8EB HCAN MD75 Message Data 75 H F8EC HCAN MD76 Message Data 76 H F8ED HCAN MD77 Message Data 77 H F8EE HCAN MD78 Message Data 78 H F8EF HCAN MD71 MD72 MD73 MD74 MD75 MD76 MD7...

Page 976: ...ATA_3 8 bits MSG_DATA_4 8 bits MSG_DATA_5 8 bits MSG_DATA_6 8 bits MSG_DATA_7 8 bits MSG_DATA_8 8 bits MD91 Message Data 91 H F8F8 HCAN MD92 Message Data 92 H F8F9 HCAN MD93 Message Data 93 H F8FA HCAN MD94 Message Data 94 H F8FB HCAN MD95 Message Data 95 H F8FC HCAN MD96 Message Data 96 H F8FD HCAN MD97 Message Data 97 H F8FE HCAN MD98 Message Data 98 H F8FF HCAN MD91 MD92 MD93 MD94 MD95 MD96 MD9...

Page 977: ...ATA_3 8 bits MSG_DATA_4 8 bits MSG_DATA_5 8 bits MSG_DATA_6 8 bits MSG_DATA_7 8 bits MSG_DATA_8 8 bits MD111 Message Data 111 H F908 HCAN MD112 Message Data 112 H F909 HCAN MD113 Message Data 113 H F90A HCAN MD114 Message Data 114 H F90B HCAN MD115 Message Data 115 H F90C HCAN MD116 Message Data 116 H F90D HCAN MD117 Message Data 117 H F90E HCAN MD118 Message Data 118 H F90F HCAN MD111 MD112 MD113...

Page 978: ...ATA_3 8 bits MSG_DATA_4 8 bits MSG_DATA_5 8 bits MSG_DATA_6 8 bits MSG_DATA_7 8 bits MSG_DATA_8 8 bits MD131 Message Data 131 H F918 HCAN MD132 Message Data 132 H F919 HCAN MD133 Message Data 133 H F91A HCAN MD134 Message Data 134 H F91B HCAN MD135 Message Data 135 H F91C HCAN MD136 Message Data 136 H F91D HCAN MD137 Message Data 137 H F91E HCAN MD138 Message Data 138 H F91F HCAN MD131 MD132 MD133...

Page 979: ...ATA_3 8 bits MSG_DATA_4 8 bits MSG_DATA_5 8 bits MSG_DATA_6 8 bits MSG_DATA_7 8 bits MSG_DATA_8 8 bits MD151 Message Data 151 H F928 HCAN MD152 Message Data 152 H F929 HCAN MD153 Message Data 153 H F92A HCAN MD154 Message Data 154 H F92B HCAN MD155 Message Data 155 H F92C HCAN MD156 Message Data 156 H F92D HCAN MD157 Message Data 157 H F92E HCAN MD158 Message Data 158 H F92F HCAN MD151 MD152 MD153...

Page 980: ...ivated by a compare match interrupt and the DISEL bit in the DTC s MRB register is 0 1 Setting condition When PWCNT PWCYR Note Only 0 can be written to clear the flag Don t care Clock Select 0 Internal clock counts on ø 1 Internal clock counts on ø 2 0 1 Internal clock counts on ø 4 0 Internal clock counts on ø 8 1 0 1 1 Internal clock counts on ø 16 Counter Start 0 PWCNT is stopped 1 PWCNT is sta...

Page 981: ...PR1 PWM Polarity Register 1 H FC04 PWM1 7 OPS1H 0 R W 6 OPS1G 0 R W 5 OPS1F 0 R W 4 OPS1E 0 R W 3 OPS1D 0 R W 0 OPS1A 0 R W 2 OPS1C 0 R W 1 OPS1B 0 R W Bit Initial value Read Write Output Polarity Select 0 PWM direct output 1 PWM inverse output PWCYR1 PWM Cycle Register 1 H FC06 PWM1 15 1 Bit Initial value Read Write Set the PWM conversion cycle 14 1 13 1 12 1 11 1 10 1 9 1 R W 8 1 R W 7 1 R W 6 1...

Page 982: ...and from PWBFR1G to PWDTR1G 14 1 13 1 12 OTS 0 R W 11 1 10 1 9 DT9 0 R W 8 DT8 0 R W 7 DT7 0 R W 6 DT6 0 R W 5 DT5 0 R W 4 DT4 0 R W 3 DT3 0 R W 2 DT2 0 R W 1 DT1 0 R W 0 DT0 0 R W Duty The data transferred to bits 9 to 0 in PWDTR1 Output Terminal Select The data transferred to bit 12 of PWDTR1 Description PWM1A output selected OTS 0 PWM1B output selected 1 PWM1C output selected 0 PWM1D output sel...

Page 983: ...ivated by a compare match interrupt and the DISEL bit in the DTC s MRB register is 0 1 Setting condition When PWCNT PWCYR Note Only 0 can be written to clear the flag Don t care Clock Select 0 Internal clock counts on ø 1 Internal clock counts on ø 2 0 1 Internal clock counts on ø 4 0 Internal clock counts on ø 8 1 0 1 1 Internal clock counts on ø 16 Counter Start 0 PWCNT is stopped 1 PWCNT is sta...

Page 984: ...PR2 PWM Polarity Register 2 H FC14 PWM2 7 OPS2H 0 R W 6 OPS2G 0 R W 5 OPS2F 0 R W 4 OPS2E 0 R W 3 OPS2D 0 R W 0 OPS2A 0 R W 2 OPS2C 0 R W 1 OPS2B 0 R W Bit Initial value Read Write Output Polarity Select 0 PWM direct output 1 PWM inverse output PWCYR2 PWM Cycle Register 2 H FC16 PWM2 15 1 Bit Initial value Read Write Set the PWM conversion cycle 14 1 13 1 12 1 11 1 10 1 9 1 R W 8 1 R W 7 1 R W 6 1...

Page 985: ... DT1 0 R W 0 DT0 0 R W Duty Comprise the data transferred to bits 9 to 0 in PWDTR2 Transfer Destination Select Selects the PWDTR2 register to which data is to be transferred Description PWDTR2A selected TDS 0 PWDTR2E selected 1 PWDTR2B selected 0 PWDTR2F selected PWDTR2C selected 1 0 PWDTR2G selected 1 PWDTR2D selected Register PWBFR2A PWBFR2B PWBFR2C PWBFR2D 0 PWDTR2H selected 1 PHDDR Port H Data...

Page 986: ...itial value Read Write PJDR Port J Data Register H FC25 Port 7 PJ7DR 0 R W 6 PJ6DR 0 R W 5 PJ5DR 0 R W 4 PJ4DR 0 R W 3 PJ3DR 0 R W 0 PJ0DR 0 R W 2 PJ2DR 0 R W 1 PJ1DR 0 R W Bit Initial value Read Write PKDR Port K Data Register H FC26 Port 7 PK7DR 0 R W 6 PK6DR 0 R W 5 Undefined 4 Undefined 3 Undefined 0 Undefined 2 Undefined 1 Undefined Bit Initial value Read Write PORTH Port H Register H FC28 Po...

Page 987: ...R 2 PJ2 R 1 PJ1 R Bit Initial value Read Write Note Determined by the state of PJ7 to PJ0 PORTK Port K Register H FC2A Port 7 PK7 R 6 PK6 R 5 Undefined 4 Undefined 3 Undefined 0 Undefined 2 Undefined 1 Undefined Bit Initial value Read Write Note Determined by state of pins PF7 and PF6 ...

Page 988: ...d COM2 can be used as ports Initial value COM4 COM3 and COM2 output the same waveform as COM1 COM4 and COM3 can be used as ports COM4 outputs the same waveform as COM3 and COM2 outputs the same waveform as COM1 COM4 can be used as a port Do not use COM4 Common Drivers Notes Note When using external expansion set a value of 0000 for SGS3 to SGS0 When the setting of SGS3 to SGS0 is 0000 COM4 to COM1...

Page 989: ...S1 0 1 0 1 0 1 Bit 0 CKS0 0 1 0 1 0 1 0 1 0 1 Notes 1 When 1 3 duty is selected the frame frequency is 4 3 times the value shown 2 This is the frame frequency when øSUB 32 768 kHz Don t care Operating Clock Frame Frequency 1 ø 20 MHz Display Data Control 0 Blank data is displayed 1 LCD RAM data is display Display Function Activate 0 LCD controller driver operation halted 1 LCD controller driver op...

Page 990: ...ng Control 0 Drive using A waveform 1 Drive using B waveform LCD LCD RAM H FC40 to H FC53 LCD MSTPCRD Module Stop Control Register D H FC60 System 7 MSTPD7 1 R W 6 MSTPD6 1 R W 5 Undefined 4 Undefined 3 Undefined 0 Undefined 2 Undefined 1 Undefined Bit Initial value Read Write Module Stop 0 Module stop mode is cleared 1 Module stop mode is set ...

Page 991: ...Shifts to sleep mode when the SLEEP instruction is executed in high speed mode or medium speed mode Shifts to sub sleep mode when the SLEEP instruction is executed in sub active mode 1 Shifts to software standby mode sub active mode and watch mode when the SLEEP instruction is executed in high speed mode or medium speed mode Shifts to watch mode or high speed mode when the SLEEP instruction is exe...

Page 992: ...terrupts by I bit Setting prohibited 1 Control of interrupts by I2 to I0 bits and IPR Setting prohibited 0 1 0 1 0 2 NMI Edge Select 0 An interrupt is requested at the falling edge of NMI input 1 An interrupt is requested at the rising edge of NMI input Interrupt Control Mode 1 and 0 Interrupt Control Mode INTM1 INTM0 Description MAC Saturation 0 Non saturating calculation for MAC instruction 1 Sa...

Page 993: ...ct 0 Specified multiplication factor is valid after transition to software standby mode watch mode or subactive mode 1 Specified multiplication factor is valid immediately after STC bits are rewritten ø Clock Output Disable System Clock Select 0 1 0 1 0 1 DDR PSTOP Hardware standby mode Software standby mode watch mode and direct transition Sleep mode and sub sleep mode High speed mode medium spee...

Page 994: ...7 MSTPA7 0 R W 6 MSTPA6 0 R W 5 MSTPA5 1 R W 4 MSTPA4 1 R W 3 MSTPA3 1 R W 0 MSTPA0 1 R W 2 MSTPA2 1 R W 1 MSTPA1 1 R W Bit Initial value Read Write Module Stop 0 Module stop mode is cleared Module stop mode is set 1 MSTPCRB Module Stop Control Register B H FDE9 System 7 MSTPB7 1 R W 6 MSTPB6 1 R W 5 1 4 MSTPB4 1 R W 3 MSTPB3 1 R W 0 MSTPB0 1 R W 2 MSTPB2 1 R W 1 MSTPB1 1 R W Bit Initial value Rea...

Page 995: ...A8 address output enabled A9 A23 address output disabled A8 A9 address output enabled A10 A23 address output disabled A8 A10 address output enabled A11 A23 address output disabled A8 A11 address output enabled A12 A23 address output disabled A8 A12 address output enabled A13 A23 address output disabled A8 A13 address output enabled A14 A23 address output disabled A8 A14 address output enabled A15 ...

Page 996: ...ode when watch mode is cancelled When the SLEEP instruction is executed in high speed mode operation shifts to watch mode or sub active mode When the SLEEP instruction is executed in sub active mode operation shifts to sub sleep mode or watch mode Operation shifts to sub active mode when watch mode is cancelled 1 Direct Transition ON Flag 0 When the SLEEP instruction is executed in high speed mode...

Page 997: ... fined 24 Unde fined R W BAA 23 23 0 R W BAA 22 22 0 R W BAA 21 21 0 R W BAA 20 20 0 R W BAA 19 19 0 R W BAA 18 18 0 R W BAA 17 17 0 R W Break Address 23 to 0 Specify the channel A or B break address BAA 16 16 0 R W 0 BAA 7 7 R W 0 BAA 6 6 R W 0 BAA 5 5 R W 0 BAA 4 4 R W 0 BAA 3 3 R W 0 BAA 2 2 R W 0 BAA 1 1 R W 0 BAA 0 0 ...

Page 998: ...ts are masked and not included in break conditions BAA3 0 lower 4 bits are masked and not included in break conditions BAA7 0 lower 8 bits are masked and not included in break conditions BAA11 0 lower 12 bits are masked and not included in break conditions BAA15 0 lower 16 bits are masked and not included in break conditions 0 1 0 1 0 1 1 0 1 0 1 0 1 Break Interrupt Enable 0 PC break interrupts ar...

Page 999: ...IRQ2SCB 0 R W 4 IRQ2SCA 0 R W 3 IRQ1SCB 0 R W 0 IRQ0SCA 0 R W 2 IRQ1SCA 0 R W 1 IRQ0SCB 0 R W Bit Initial value Read Write ISCRL IRQ5 to IRQ0 sense control A and B Description IRQ5SCB to IRQ0SCB IRQ5SCA to IRQ0SCA 0 1 0 1 0 1 Interrupt request generated at IRQ5 to IRQ0 input at low level Interrupt request generated at falling edge of IRQ5 to IRQ0 input Interrupt request generated at rising edge of...

Page 1000: ...t exception handling is executed while low level detection is set IRQnSCB IRQnSCA 0 and IRQn input is high When IRQn interrupt exception handling is executed while falling rising or both edge detection is set IRQnSCB 1 or IRQnSCA 1 When the DTC is activated by an IRQn interrupt and the DISEL bit in MRB of the DTC is cleared to 0 1 Setting conditions When IRQn input goes low when low level detectio...

Page 1001: ...C DTC DTC DTC DTC DTC DTC 7 DTCE7 0 R W 6 DTCE6 0 R W 5 DTCE5 0 R W 4 DTCE4 0 R W 3 DTCE3 0 R W 0 DTCE0 0 R W 2 DTCE2 0 R W 1 DTCE1 0 R W Bit Initial value Read Write DTC Activation Enable 0 DTC activation by interrupt is disabled Clearing conditions When the DISEL bit is 1 and the data transfer has ended When the specified number of transfers have ended 1 DTC activation by interrupt is enabled Ho...

Page 1002: ... Clearing condition When the DISEL bit is 0 and the specified number of transfers have not ended When 0s written to the DISEL bit after a software activated data transfer end interrupt SWDTEND request has been sent to the CPU 1 DTC software activation is enabled Holding conditions When the DISEL bit is 1 and data transfer has ended When the specified number of transfers have ended During data tran...

Page 1003: ...re match in TPU channel 3 0 1 0 1 Group 1 Compare Match Select 0 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 0 1 0 1 Group 2 Compare Match Select 0 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 0 1 0 1 Group 3 Compare Match Select 0 1 Com...

Page 1004: ...oup 2 independent 1 and 0 output at compare match A or B in the selected TPU channel 1 Group 3 Non Overlap 0 Normal operation in pulse output group 3 output values updated at compare match A in the selected TPU channel Non overlapping operation in pulse output group 3 independent 1 and 0 output at compare match A or B in the selected TPU channel 1 Group 3 Inversion 0 Inverted output for pulse outp...

Page 1005: ...a Enable Register L H FE29 PPG 7 NDER7 0 R W 6 NDER6 0 R W 5 NDER5 0 R W 4 NDER4 0 R W 3 NDER3 0 R W 0 NDER0 0 R W 2 NDER2 0 R W 1 NDER1 0 R W Bit Initial value Read Write Next Data Enable 0 Pulse outputs PO7 to PO0 are disabled NDR7 to NDR0 are not transferred to POD7 to POD0 Pulse outputs PO7 to PO0 are enabled NDR7 to NDR0 are transferred to POD7 to POD0 1 PODRH Output Data Register H H FE2A PP...

Page 1006: ... Register L H FE2B PPG 7 POD7 0 R W 6 POD6 0 R W 5 POD5 0 R W 4 POD4 0 R W 3 POD3 0 R W 0 POD0 0 R W 2 POD2 0 R W 1 POD1 0 R W Bit Initial value Read Write Note A bit that has been set for pulse output by NDER is read only ...

Page 1007: ... 0 1 2 1 1 1 Bit Initial value Read Write Address H FE2E Same Trigger for Pulse Output Groups 7 NDR15 0 R W 6 NDR14 0 R W 5 NDR13 0 R W 4 NDR12 0 R W 3 1 0 1 2 1 1 1 Bit Initial value Read Write Address H FE2C 7 1 6 1 5 1 4 1 3 NDR11 0 R W 0 NDR8 0 R W 2 NDR10 0 R W 1 NDR9 0 R W Bit Initial value Read Write Address H FE2E Different Triggers for Pulse Output Groups Note For details see section 11 2...

Page 1008: ... 0 1 2 1 1 1 Bit Initial value Read Write Address H FE2F Same Trigger for Pulse Output Groups 7 NDR7 0 R W 6 NDR6 0 R W 5 NDR5 0 R W 4 NDR4 0 R W 3 1 0 1 2 1 1 1 Bit Initial value Read Write Address H FE2D 7 1 6 1 5 1 4 1 3 NDR3 0 R W 0 NDR0 0 R W 2 NDR2 0 R W 1 NDR1 0 R W Bit Initial value Read Write Address H FE2F Different Triggers for Pulse Output Groups Note For details see section 11 2 4 Not...

Page 1009: ...2DDR 0 W 1 P21DDR 0 W Bit Initial value Read Write Specify input or output for each of the pins in port 2 P3DDR Port 3 Data Direction Register H FE32 Port 7 P37DDR 0 W 6 P36DDR 0 W 5 P35DDR 0 W 4 P34DDR 0 W 3 P33DDR 0 W 0 P30DDR 0 W 2 P32DDR 0 W 1 P31DDR 0 W Bit Initial value Read Write Specify input or output for each of the pins in port 3 P5DDR Port 5 Data Direction Register H FE34 Port 7 Undefi...

Page 1010: ...R 0 W 1 PB1DDR 0 W Bit Initial value Read Write Specify input or output for each of the pins in port B PCDDR Port C Data Direction Register H FE3B Port 7 PC7DDR 0 W 6 PC6DDR 0 W 5 PC5DDR 0 W 4 PC4DDR 0 W 3 PC3DDR 0 W 0 PC0DDR 0 W 2 PC2DDR 0 W 1 PC1DDR 0 W Bit Initial value Read Write Specify input or output for each of the pins in port C PDDDR Port D Data Direction Register H FE3C Port 7 PD7DDR 0 ...

Page 1011: ...6 Initial value Read Write Mode 7 Initial value Read Write Specify input or output for each of the pins in port F PAPCR Port A MOS Pull Up Control Register H FE40 Port 7 PA7PCR 0 R W 6 PA6PCR 0 R W 5 PA5PCR 0 R W 4 PA4PCR 0 R W 3 PA3PCR 0 R W 0 PA0PCR 0 R W 2 PA2PCR 0 R W 1 PA1PCR 0 R W Bit Initial value Read Write Control the MOS input pull up function incorporated into port A PBPCR Port B MOS Pu...

Page 1012: ... 1 PD1PCR 0 R W Bit Initial value Read Write Control the MOS input pull up function incorporated into port D PEPCR Port E MOS Pull Up Control Register H FE44 Port 7 PE7PCR 0 R W 6 PE6PCR 0 R W 5 PE5PCR 0 R W 4 PE4PCR 0 R W 3 PE3PCR 0 R W 0 PE0PCR 0 R W 2 PE2PCR 0 R W 1 PE1PCR 0 R W Bit Initial value Read Write Control the MOS input pull up function incorporated into port E P3ODR Port 3 Open Drain ...

Page 1013: ...ontrol Register H FE48 Port 7 PB7ODR 0 R W 6 PB6ODR 0 R W 5 PB5ODR 0 R W 4 PB4ODR 0 R W 3 PB3ODR 0 R W 0 PB0ODR 0 R W 2 PB2ODR 0 R W 1 PB1ODR 0 R W Bit Initial value Read Write Control whether PMOS is on or off for each port B pin PCODR Port C Open Drain Control Register H FE49 Port 7 PC7ODR 0 R W 6 PC6ODR 0 R W 5 PC5ODR 0 R W 4 PC4ODR 0 R W 3 PC3ODR 0 R W 0 PC0ODR 0 R W 2 PC2ODR 0 R W 1 PC1ODR 0 ...

Page 1014: ...r another channel performing synchronous clearing synchronous operation 1 TCNT clearing disabled TCNT cleared by TGRC compare match input capture 2 TCNT cleared by TGRD compare match input capture 2 TCNT cleared by counter clearing for another channel performing synchronous clearing synchronous operation 1 0 1 0 1 0 1 1 0 1 0 1 0 1 Notes 1 2 Synchronous operation setting is performed by setting th...

Page 1015: ...eration 1 Buffer Operation B 0 TGRB operates normally TGRB and TGRD used together for buffer operation 1 Notes 1 2 MD3 is a reserved bit In a write it should always be written with 0 Phase counting mode cannot be set for channel 3 In this case 0 should always be written to MD2 Mode 0 Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 P...

Page 1016: ...input source is TIOCA3 pin Capture input source is channel 4 count clock 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Don t care TGR3B I O Control 0 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges I...

Page 1017: ...e match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT4 count up count down 1 TGR3D is output compare register 2 TGR3D is input capture register 2 Output disabled Initial output is 0 output Output disabled Initial output is 1 output Capture input source i...

Page 1018: ... TGFB bit disabled Interrupt requests TGIB by TGFB bit enabled 1 TGR Interrupt Enable C 0 Interrupt requests TGIC by TGFC bit disabled Interrupt requests TGIC by TGFC bit enabled 1 TGR Interrupt Enable D 0 Interrupt requests TGID by TGFD bit disabled Interrupt requests TGID by TGFD bit enabled 1 Overflow Interrupt Enable 0 Interrupt requests TCIV by TCFV disabled Interrupt requests TCIV by TCFV en...

Page 1019: ...put capture signal while TGRB is functioning as input capture register Input Capture Output Compare Flag C 0 Clearing conditions When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFC after reading TGFC 1 1 Setting conditions When TCNT TGRC while TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture sign...

Page 1020: ... W 0 0 R W 2 0 R W 1 0 R W Up counter TGR3A Timer General Register 3A H FE88 TPU3 TGR3B Timer General Register 3B H FE8A TPU3 TGR3C Timer General Register 3C H FE8C TPU3 TGR3D Timer General Register 3D H FE8E TPU3 15 1 R W 14 1 R W 13 1 R W 12 1 R W 11 1 R W 8 1 R W 10 1 R W 9 1 R W Bit Initial value Read Write 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W ...

Page 1021: ... compare match input capture TCNT cleared by TGRB compare match input capture TCNT cleared by counter clearing for another channel performing synchronous clearing synchronous operation 0 1 0 1 0 1 Note Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1 Note Bit 7 is reserved in channel 4 It is always read as 0 and cannot be modified Note This setting is ignored when ch...

Page 1022: ...1 MD1 0 R W Bit Initial value Read Write Don t care Note MD3 is a reserved bit In a write it should always be written with 0 Mode 0 Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ...

Page 1023: ...ut is 0 output Output disabled Initial output is 1 output Capture input source is TIOCA4 pin Capture input source is TGR3A compare match input capture 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Don t care TGR4B I O Control 0 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capt...

Page 1024: ...d 1 TGR Interrupt Enable B 0 Interrupt requests TGIB by TGFB bit disabled Interrupt requests TGIB by TGFB bit enabled 1 Overflow Interrupt Enable 0 Interrupt requests TCIV by TCFV disabled Interrupt requests TCIV by TCFV enabled 1 Underflow Interrupt Enable 0 Interrupt requests TCIU by TCFU disabled Interrupt requests TCIU by TCFU enabled 1 A D Conversion Start Request Enable 0 A D conversion star...

Page 1025: ...aring conditions When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFB after reading TGFB 1 1 Setting conditions When TCNT TGRB while TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Overflow Flag 0 Clearing condition When 0 is written to T...

Page 1026: ...These counters can be used as up down counters only in phase counting mode or when counting overflow underflow on another channel In other cases they function as up counters TGR4A Timer General Register 4A H FE98 TPU4 TGR4B Timer General Register 4B H FE9A TPU4 15 1 R W 14 1 R W 13 1 R W 12 1 R W 11 1 R W 8 1 R W 10 1 R W 9 1 R W Bit Initial value Read Write 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W...

Page 1027: ...0 0 R W 2 TPSC2 0 R W 1 TPSC1 0 R W Clock Edge 0 1 Count at rising edge Count at falling edge Count at both edges 0 1 Counter Clear TCNT clearing disabled TCNT cleared by TGRA compare match input capture TCNT cleared by TGRB compare match input capture TCNT cleared by counter clearing for another channel performing synchronous clearing synchronous operation 0 1 0 1 0 1 Note Synchronous operation s...

Page 1028: ...1 MD1 0 R W Bit Initial value Read Write Don t care Note MD3 is a reserved bit In a write it should always be written with 0 Mode 0 Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ...

Page 1029: ...r TGR5A is input capture register Output disabled Initial output is 0 output Output disabled Initial output is 1 output Capture input source is TIOCA5 pin 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Don t care TGR5B I O Control 0 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capt...

Page 1030: ...d 1 TGR Interrupt Enable B 0 Interrupt requests TGIB by TGFB bit disabled Interrupt requests TGIB by TGFB bit enabled 1 Overflow Interrupt Enable 0 Interrupt requests TCIV by TCFV disabled Interrupt requests TCIV by TCFV enabled 1 Underflow Interrupt Enable 0 Interrupt requests TCIU by TCFU disabled Interrupt requests TCIU by TCFU enabled 1 A D Conversion Start Request Enable 0 A D conversion star...

Page 1031: ...aring conditions When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFB after reading TGFB 1 1 Setting conditions When TCNT TGRB while TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Overflow Flag 0 Clearing condition When 0 is written to T...

Page 1032: ...R W 14 1 R W 13 1 R W 12 1 R W 11 1 R W 8 1 R W 10 1 R W 9 1 R W Bit Initial value Read Write 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W TSTR Timer Start Register H FEB0 TPU 7 0 6 0 5 CST5 0 R W 4 CST4 0 R W 3 CST3 0 R W 0 CST0 0 R W 2 CST2 0 R W 1 CST1 0 R W Bit Initial value Read Write n 5 to 0 Counter Start 0 TCNTn count operation is stopped TCNTn performs count operation 1...

Page 1033: ...s independently TCNT presetting clearing is unrelated to other channels TCNTn performs synchronous operation TCNT synchronous presetting synchronous clearing is possible 1 Notes 1 2 To set synchronous operation the SYNC bits for at least two channels must be set to 1 To set synchronous clearing in addition to the SYNC bit the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in...

Page 1034: ... INT INT INT INT INT INT INT INT INT 7 0 6 IPR6 1 R W 5 IPR5 1 R W 4 IPR4 1 R W 3 0 0 IPR0 1 R W 2 IPR2 1 R W 1 IPR1 1 R W Bit Initial value Read Write Correspondence between Interrupt Sources and IPR Settings Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRJ IPRK IPRM Bits 6 to 4 IRQ0 IRQ2 IRQ3 1 Watchdog timer 0 PC break TPU channel 0 TPU channel 2 TPU channel 4 1 SCI channel 1 PWM channel 1...

Page 1035: ...Area n is designated for 16 bit access Area n is designated for 8 bit access 1 n 7 to 0 ASTCR Access State Control Register H FED1 Bus Controller 7 AST7 1 R W 6 AST6 1 R W 5 AST5 1 R W 4 AST4 1 R W 3 AST3 1 R W 0 AST0 1 R W 2 AST2 1 R W 1 AST1 1 R W Bit Initial value Read Write Area 7 to 0 Access State Control 0 Area n is designated for 2 state access Wait state insertion in area n external space ...

Page 1036: ... 0 1 program wait state inserted when external space area 7 is accessed 1 1 2 program wait states inserted when external space area 7 is accessed 0 3 program wait states inserted when external space area 7 is accessed 1 0 Program wait not inserted when external space area 6 is accessed 0 1 program wait state inserted when external space area 6 is accessed 1 1 2 program wait states inserted when ex...

Page 1037: ... 0 1 program wait state inserted when external space area 3 is accessed 1 1 2 program wait states inserted when external space area 3 is accessed 0 3 program wait states inserted when external space area 3 is accessed 1 0 Program wait not inserted when external space area 2 is accessed 0 1 program wait state inserted when external space area 2 is accessed 1 1 2 program wait states inserted when ex...

Page 1038: ...s 1 state Burst cycle comprises 2 states 1 Burst ROM Enable 0 Area 0 is basic bus interface Area 0 is burst ROM interface 1 Idle Cycle Insert 0 0 Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles 1 0 1 Idle Cycle Insert 1 Idle cycle not inserted in case of successive external read ...

Page 1039: ...RAM Emulation Register H FEDB Flash Memory 7 0 R 6 0 R 5 0 R W 4 0 R W 3 RAMS 0 R W 0 RAM0 0 R W 2 RAM2 0 R W 1 RAM1 0 R W Bit Initial value Read Write RAM Select 0 Emulation not selected Program erase protection of all flash memory blocks is disabled 1 Emulation selected Program erase protection of all flash memory blocks is enabled Flash Memory Area Selection H FFE000 H FFE3FF H 000000 H 0003FF ...

Page 1040: ...l value Read Write P3DR Port 3 Data Register H FF02 Port 7 P37DR 0 R W 6 P36DR 0 R W 5 P35DR 0 R W 4 P34DR 0 R W 3 P33DR 0 R W 0 P30DR 0 R W 2 P32DR 0 R W 1 P31DR 0 R W Bit Initial value Read Write P5DR Port 5 Data Register H FF04 Port 7 Undefined 6 Undefined 5 Undefined 4 Undefined 3 Undefined 0 P50DR 0 R W 2 P52DR 0 R W 1 P51DR 0 R W Bit Initial value Read Write PADR Port A Data Register H FF09 ...

Page 1041: ... value Read Write PDDR Port D Data Register H FF0C Port 7 PD7DR 0 R W 6 PD6DR 0 R W 5 PD5DR 0 R W 4 PD4DR 0 R W 3 PD3DR 0 R W 0 PD0DR 0 R W 2 PD2DR 0 R W 1 PD1DR 0 R W Bit Initial value Read Write PEDR Port E Data Register H FF0D Port 7 PE7DR 0 R W 6 PE6DR 0 R W 5 PE5DR 0 R W 4 PE4DR 0 R W 3 PE3DR 0 R W 0 PE0DR 0 R W 2 PE2DR 0 R W 1 PE1DR 0 R W Bit Initial value Read Write PFDR Port F Data Registe...

Page 1042: ...er clearing for another channel performing synchronous clearing synchronous operation 1 TCNT clearing disabled TCNT cleared by TGRC compare match input capture 2 TCNT cleared by TGRD compare match input capture 2 TCNT cleared by counter clearing for another channel performing synchronous clearing synchronous operation 1 0 1 0 1 0 1 1 0 1 0 1 0 1 Notes 1 2 Synchronous operation setting is performed...

Page 1043: ...peration 1 Buffer Operation B 0 TGRB operates normally TGRB and TGRD used together for buffer operation 1 Notes 1 2 MD3 is a reserved bit In a write it should always be written with 0 Phase counting mode cannot be set for channel 0 In this case 0 should always be written to MD2 Mode 0 Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 ...

Page 1044: ...input source is TIOCA0 pin Capture input source is channel 1 count clock 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Don t care TGR0B I O Control 0 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges I...

Page 1045: ...re match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT1 count up count down 1 TGR0D is output compare register 2 TGR0D is input capture register 2 Output disabled Initial output is 0 output Output disabled Initial output is 1 output Capture input source ...

Page 1046: ...y TGFB bit disabled Interrupt requests TGIB by TGFB bit enabled 1 TGR Interrupt Enable C 0 Interrupt requests TGIC by TGFC bit disabled Interrupt requests TGIC by TGFC bit enabled 1 TGR Interrupt Enable D 0 Interrupt requests TGID by TGFD bit disabled Interrupt requests TGID by TGFD bit enabled 1 Overflow Interrupt Enable 0 Interrupt requests TCIV by TCFV disabled Interrupt requests TCIV by TCFV e...

Page 1047: ...put capture signal while TGRB is functioning as input capture register Input Capture Output Compare Flag C 0 Clearing conditions When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFC after reading TGFC 1 1 Setting conditions When TCNT TGRC while TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture sign...

Page 1048: ... W 0 0 R W 2 0 R W 1 0 R W Up counter TGR0A Timer General Register 0A H FF18 TPU0 TGR0B Timer General Register 0B H FF1A TPU0 TGR0C Timer General Register 0C H FF1C TPU0 TGR0D Timer General Register 0D H FF1E TPU0 15 1 R W 14 1 R W 13 1 R W 12 1 R W 11 1 R W 8 1 R W 10 1 R W 9 1 R W Bit Initial value Read Write 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W ...

Page 1049: ... compare match input capture TCNT cleared by TGRB compare match input capture TCNT cleared by counter clearing for another channel performing synchronous clearing synchronous operation 0 1 0 1 0 1 Note Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1 Note This setting is ignored when channel 1 is in phase counting mode 7 0 6 CCLR1 0 R W 5 CCLR0 0 R W 4 CKEG1 0 R W 3 ...

Page 1050: ... 1 MD1 0 R W Bit Initial value Read Write Don t care Note MD3 is a reserved bit In a write it should always be written with 0 Mode 0 Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ...

Page 1051: ...l output is 0 output Output disabled Initial output is 1 output Capture input source is TIOCA1 pin Capture input source is TGR0A compare match input capture 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Don t care TGR1B I O Control 0 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Inpu...

Page 1052: ...ed 1 TGR Interrupt Enable B 0 Interrupt requests TGIB by TGFB bit disabled Interrupt requests TGIB by TGFB bit enabled 1 Overflow Interrupt Enable 0 Interrupt requests TCIV by TCFV disabled Interrupt requests TCIV by TCFV enabled 1 Underflow Interrupt Enable 0 Interrupt requests TCIU by TCFU disabled Interrupt requests TCIU by TCFU enabled 1 A D Conversion Start Request Enable 0 A D conversion sta...

Page 1053: ...earing conditions When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFB after reading TGFB 1 1 Setting conditions When TCNT TGRB while TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Overflow Flag 0 Clearing condition When 0 is written to ...

Page 1054: ...These counters can be used as up down counters only in phase counting mode or when counting overflow underflow on another channel In other cases they function as up counters TGR1A Timer General Register 1A H FF28 TPU1 TGR1B Timer General Register 1B H FF2A TPU1 15 1 R W 14 1 R W 13 1 R W 12 1 R W 11 1 R W 8 1 R W 10 1 R W 9 1 R W Bit Initial value Read Write 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W...

Page 1055: ...TGRA compare match input capture TCNT cleared by TGRB compare match input capture TCNT cleared by counter clearing for another channel performing synchronous clearing synchronous operation 0 1 0 1 0 1 Note Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1 Note This setting is ignored when channel 2 is in phase counting mode 7 0 6 CCLR1 0 R W 5 CCLR0 0 R W 4 CKEG1 0 R ...

Page 1056: ... 1 MD1 0 R W Bit Initial value Read Write Don t care Note MD3 is a reserved bit In a write it should always be written with 0 Mode 0 Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ...

Page 1057: ...er TGR2A is input capture register Output disabled Initial output is 0 output Output disabled Initial output is 1 output Capture input source is TIOCA2 pin 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Don t care TGR2B I O Control 0 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input cap...

Page 1058: ...ed 1 TGR Interrupt Enable B 0 Interrupt requests TGIB by TGFB bit disabled Interrupt requests TGIB by TGFB bit enabled 1 Overflow Interrupt Enable 0 Interrupt requests TCIV by TCFV disabled Interrupt requests TCIV by TCFV enabled 1 Underflow Interrupt Enable 0 Interrupt requests TCIU by TCFU disabled Interrupt requests TCIU by TCFU enabled 1 A D Conversion Start Request Enable 0 A D conversion sta...

Page 1059: ...earing conditions When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFB after reading TGFB 1 1 Setting conditions When TCNT TGRB while TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Overflow Flag 0 Clearing condition When 0 is written to ...

Page 1060: ...These counters can be used as up down counters only in phase counting mode or when counting overflow underflow on another channel In other cases they function as up counters TGR2A Timer General Register 2A H FF38 TPU2 TGR2B Timer General Register 2B H FF3A TPU2 15 1 R W 14 1 R W 13 1 R W 12 1 R W 11 1 R W 8 1 R W 10 1 R W 9 1 R W Bit Initial value Read Write 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W...

Page 1061: ... 0 TCNT is initialized to H 00 and halted TCNT counts 1 Timer Mode Select 0 Interval timer mode WDT0 requests an interval timer interrupt WOVI from the CPU when the TCNT overflows Watchdog timer mode A reset is issued when the TCNT overflows if the RSTE bit of RSTCSR is set to 1 1 Overflow Flag 0 Clearing conditions Cleared when 0 is written to the TME bit Only applies to WDT1 Cleared by reading T...

Page 1062: ...4 1 3 1 0 1 2 1 1 1 Reset Enable 0 Reset signal is not generated if TCNT overflows Reset signal is generated if TCNT overflows 1 Watchdog Overflow Flag 0 Clearing condition Cleared by reading TCSR when WOVF 1 then writing 0 to WOVF Setting condition Set when TCNT overflows changed from H FF to H 00 during watchdog timer operation 1 Note Can only be written with 0 for flag clearing RSTCSR is write ...

Page 1063: ...sabled 1 Multiprocessor format selected Parity Mode 0 Even parity 3 Odd parity 4 1 Parity Enable 0 Parity bit addition and checking disabled Parity bit addition and checking enabled 2 1 Character Length 0 8 bit data 7 bit data 1 1 Communication Mode 0 Asynchronous mode Synchronous mode 1 1 stop bit In transmission a single 1 bit stop bit is added to the end of a transmit character before it is sen...

Page 1064: ... When even parity is set parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even In reception a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even 4 When odd parity is set parity bit addition is performed in transmission so that the total number of 1 bits in t...

Page 1065: ...ction and automatic data retransmission performed TXI interrupt generated by TEND flag TEND flag set 12 5 etu after start of transmission 11 0 etu in GSM mode Block transfer mode operation Error signal transmission detection and automatic data retransmission not performed TXI interrupt generated by TDRE flag TEND flag set 11 5 etu after start of transmission 11 0 etu in GSM mode 1 GSM Mode 0 Norma...

Page 1066: ...is even In reception a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even 3 When odd parity is set parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd In reception a check is performed to see if the total number of 1 bits in the receive character plus the p...

Page 1067: ...ransmit End Interrupt Enable 0 Transmit end interrupt TEI request disabled 8 1 Transmit end interrupt TEI request enabled 8 Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled normal reception mode performed Clearing conditions When the MPIE bit is cleared to 0 When MPB 1 data is received 1 Multiprocessor interrupts enabled 7 Receive interrupt RXI requests receive error interrupt ...

Page 1068: ...in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode SMR setting must be performed to decide the transfer format before setting the RE bit to 1 7 When receive data including MPB 0 is received receive data transfer from RSR to RDR receive error detection and setting of the RDRF FER and ORER flags in SSR is not performed When r...

Page 1069: ...erates as port I O pin Outputs clock as SCK output pin Operates as SCK output pin with output fixed low Outputs clock as SCK output pin Operates as SCK output pin with output fixed high Outputs clock as SCK output pin 0 1 See the SCI 0 1 0 1 0 1 0 1 0 1 Operate in the same way as for the nomal SCI TDR0 Transmit Data Register 0 H FF7B SCI0 Smart Card Interface 0 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 ...

Page 1070: ...mber of 1 bits in the receive data plus the parity bit does not match the parity setting even or odd specified by the O E bit in SMR 6 Framing Error 0 Clearing condition When 0 is written in FER after reading FER 1 1 Setting condition When the SCI checks whether the stop bit at the end of the receive data when reception ends and the stop bit is 0 4 Overrun Error 0 Clearing condition When 0 is writ...

Page 1071: ...cannot be continued while the FER flag is set to 1 In clocked synchronous mode serial transmission cannot be continued either 5 The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0 6 If a parity error occurs the receive data is transferred to RDR but the RDRF flag is not set Also subsequent serial reception cannot be continued while the PER flag is set...

Page 1072: ...it in SCR to 0 does not affect the ERS flag which retains its previous state Error Signal Status 0 Normal reception with no error signal Clearing condition Upon reset and in standby mode or module stop mode When 0 is written to ERS after reading ERS 1 1 Error signal sent from receiver indicating detection of parity error Setting condition When the low level of the error signal is sampled RDR0 Rece...

Page 1073: ... Smart card interface function enabled Smart Card Data Invert 0 TDR contents are transmitted without modification Receive data is stored in RDR without modification 1 TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Smart Card Data Transfer Direction 0 TDR contents are transmitted LSB first Receive data is stored in RDR LSB first 1 TDR contents are ...

Page 1074: ...format selected Parity Mode 0 Even parity 3 Odd parity 4 1 Parity Enable 0 Parity bit addition and checking disabled Parity bit addition and checking enabled 2 1 Character Length 0 8 bit data 7 bit data 1 1 Communication Mode 0 Asynchronous mode Clocked synchronous mode 1 Stop Bit Length 0 1 1 stop bit In transmission a single 1 bit stop bit is added to the end of a transmit character before it is...

Page 1075: ... When even parity is set parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even In reception a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even 4 When odd parity is set parity bit addition is performed in transmission so that the total number of 1 bits in t...

Page 1076: ...ction and automatic data retransmission performed TXI interrupt generated by TEND flag TEND flag set 12 5 etu after start of transmission 11 0 etu in GSM mode Block transfer mode operation Error signal transmission detection and automatic data retransmission not performed TXI interrupt generated by TDRE flag TEND flag set 11 5 etu after start of transmission 11 0 etu in GSM mode 1 GSM Mode 0 Norma...

Page 1077: ...is even In reception a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even 3 When odd parity is set parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd In reception a check is performed to see if the total number of 1 bits in the receive character plus the p...

Page 1078: ...ransmit End Interrupt Enable 0 Transmit end interrupt TEI request disabled 8 1 Transmit end interrupt TEI request enabled 8 Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled normal reception mode performed Clearing conditions When the MPIE bit is cleared to 0 When MPB 1 data is received 1 Multiprocessor interrupts enabled 7 Receive interrupt RXI requests receive error interrupt ...

Page 1079: ...in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode SMR setting must be performed to decide the transfer format before setting the RE bit to 1 7 When receive data including MPB 0 is received receive data transfer from RSR to RDR receive error detection and setting of the RDRF FER and ORER flags in SSR is not performed When r...

Page 1080: ...rates as port I O pin Outputs clock as SCK output pin Operates as SCK output pin with output fixed low Outputs clock as SCK output pin Operates as SCK output pin with output fixed high Outputs clock as SCK output pin 0 1 See the SCI 0 1 0 1 0 1 0 1 0 1 Operate in the same way as for the normal SCI TDR1 Transmit Data Register 1 H FF83 SCI1 Smart Card Interface 1 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 ...

Page 1081: ...mber of 1 bits in the receive data plus the parity bit does not match the parity setting even or odd specified by the O E bit in SMR 6 Framing Error 0 Clearing condition When 0 is written in FER after reading FER 1 1 Setting condition When the SCI checks whether the stop bit at the end of the receive data when reception ends and the stop bit is 0 Overrun Error 0 Clearing condition When 0 is writte...

Page 1082: ...cannot be continued while the FER flag is set to 1 In clocked synchronous mode serial transmission cannot be continued either 5 The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0 6 If a parity error occurs the receive data is transferred to RDR but the RDRF flag is not set Also subsequent serial reception cannot be continued while the PER flag is set...

Page 1083: ...atus 0 Normal reception with no error signal Clearing condition Upon reset and in standby mode or module stop mode When 0 is written to ERS after reading ERS 1 1 Error signal sent from receiver indicating detection of parity error Setting condition When the low level of the error signal is sampled Operate in the same way as for the normal SCI Operate in the same way as for the normal SCI RDR1 Rece...

Page 1084: ... Smart card interface function enabled Smart Card Data Invert 0 TDR contents are transmitted without modification Receive data is stored in RDR without modification 1 TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Smart Card Data Transfer Direction 0 TDR contents are transmitted LSB first Receive data is stored in RDR LSB first 1 TDR contents are ...

Page 1085: ...format selected Parity Mode 0 Even parity 3 Odd parity 4 1 Parity Enable 0 Parity bit addition and checking disabled Parity bit addition and checking enabled 2 1 Character Length 0 8 bit data 7 bit data 1 1 Communication Mode 0 Asynchronous mode Clocked synchronous mode 1 Stop Bit Length 0 1 1 stop bit In transmission a single 1 bit stop bit is added to the end of a transmit character before it is...

Page 1086: ... When even parity is set parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even In reception a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even 4 When odd parity is set parity bit addition is performed in transmission so that the total number of 1 bits in t...

Page 1087: ...ction and automatic data retransmission performed TXI interrupt generated by TEND flag TEND flag set 12 5 etu after start of transmission 11 0 etu in GSM mode Block transfer mode operation Error signal transmission detection and automatic data retransmission not performed TXI interrupt generated by TDRE flag TEND flag set 11 5 etu after start of transmission 11 0 etu in GSM mode 1 GSM Mode 0 Norma...

Page 1088: ...is even In reception a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even 3 When odd parity is set parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd In reception a check is performed to see if the total number of 1 bits in the receive character plus the p...

Page 1089: ...ransmit End Interrupt Enable 0 Transmit end interrupt TEI request disabled 8 1 Transmit end interrupt TEI request enabled 8 Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled normal reception mode performed Clearing conditions When the MPIE bit is cleared to 0 When MPB 1 data is received 1 Multiprocessor interrupts enabled 7 Receive interrupt RXI requests receive error interrupt ...

Page 1090: ...in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode SMR setting must be performed to decide the transfer format before setting the RE bit to 1 7 When receive data including MPB 0 is received receive data transfer from RSR to RDR receive error detection and setting of the RDRF FER and ORER flags in SSR is not performed When r...

Page 1091: ...rates as port I O pin Outputs clock as SCK output pin Operates as SCK output pin with output fixed low Outputs clock as SCK output pin Operates as SCK output pin with output fixed high Outputs clock as SCK output pin 0 1 See the SCI 0 1 0 1 0 1 0 1 0 1 Operate in the same way as for the normal SCI TDR2 Transmit Data Register 2 H FF8B SCI2 Smart Card Interface 2 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 ...

Page 1092: ...mber of 1 bits in the receive data plus the parity bit does not match the parity setting even or odd specified by the O E bit in SMR 6 Framing Error 0 Clearing condition When 0 is written in FER after reading FER 1 1 Setting condition When the SCI checks whether the stop bit at the end of the receive data when reception ends and the stop bit is 0 Overrun Error 0 Clearing condition When 0 is writte...

Page 1093: ...cannot be continued while the FER flag is set to 1 In clocked synchronous mode serial transmission cannot be continued either 5 The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0 6 If a parity error occurs the receive data is transferred to RDR but the RDRF flag is not set Also subsequent serial reception cannot be continued while the PER flag is set...

Page 1094: ...atus 0 Normal reception with no error signal Clearing condition Upon reset and in standby mode or module stop mode When 0 is written to ERS after reading ERS 1 1 Error signal sent from receiver indicating detection of parity error Setting condition When the low level of the error signal is sampled Operate in the same way as for the normal SCI Operate in the same way as for the normal SCI RDR2 Rece...

Page 1095: ...are inverted before being transmitted Receive data is stored in RDR in inverted form Smart Card Data Transfer Direction 0 TDR contents are transmitted LSB first Receive data is stored in RDR LSB first 1 TDR contents are transmitted MSB first Receive data is stored in RDR MSB first ADDRA A D Data Register A H FF90 A D Converter ADDRB A D Data Register B H FF92 A D Converter ADDRC A D Data Register ...

Page 1096: ...de When A D conversion ends on all specified channels A D Start 0 A D conversion stopped 1 Single mode A D conversion is started Cleared to 0 automatically when conversion on the specified channel ends Scan mode A D conversion is started Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software a reset or a transition to standby mode or module stop mode Chan...

Page 1097: ...igger Select 0 A D conversion start by software is enabled A D conversion start by TPU conversion start trigger is enabled Setting prohibited A D conversion start by external trigger pin ADTRG is enabled 0 1 1 0 1 Clock Select 0 Conversion time 530 states max Conversion time 266 states max Conversion time 134 states max Conversion time 68 states max 0 1 1 0 1 ...

Page 1098: ...er PSM The TCNT counts frequency division clock pulses of the ø SUB based prescaler PSS 1 Reset or NMI 0 NMI request Internal reset request 1 Clock Select 2 to 0 ø 2 ø 64 ø 128 ø 512 ø 2048 ø 8192 ø 32768 ø 131072 øSUB 2 øSUB 4 øSUB 8 øSUB 16 øSUB 32 øSUB 64 øSUB 128 øSUB 256 25 6 µs 819 2 µs 1 6 ms 6 6 ms 26 2 ms 104 9 ms 419 4 ms 1 68 s 15 6 ms 31 3 ms 62 5 ms 125 ms 250 ms 500 ms 1 s 2 s 0 CKS2...

Page 1099: ... R WDT1 7 0 R W 6 0 R W 5 0 R W 4 0 R W 3 0 R W 0 0 R W 2 0 R W 1 0 R W Bit Initial value Read Write Up counter Note TCNT is write protected by a password to prevent accidental overwriting For details see section 12 2 4 Notes on Register Access ...

Page 1100: ...tion to program verify mode Setting condition When FWE 1 and SWE 1 Erase verify 0 Erase verify mode cleared 1 Transition to erase verify mode Setting condition When FWE 1 and SWE 1 Note Determined by the state of the FWE pin Program Setup Bit 0 Program setup cleared Program setup Setting condition When FWE 1 and SWE 1 1 Erase Setup Bit 0 Erase setup cleared Erase setup Setting condition When FWE 1...

Page 1101: ...ory Error 0 Flash memory is operating normally Flash memory program erase protection error protection is disabled Clearing condition Power on reset or hardware standby mode 1 An error has occurred during flash memory programming erasing Flash memory program erase protection error protection is enabled Setting condition See section 20 8 3 Error Protection ...

Page 1102: ... area Block Size Addresses EB0 1 kB EB1 1 kB EB2 1 kB EB3 1 kB EB4 28 kB EB5 16 kB EB6 8 kB EB7 8 kB EB8 32 kB EB9 32 kB H 000000 H 0003FF H 000400 H 0007FF H 000800 H 000BFF H 000C00 H 000FFF H 001000 H 007FFF H 008000 H 00BFFF H 00C000 H 00DFFF H 00E000 H 00FFFF H 010000 H 017FFF H 018000 H 01FFFF FLPWCR Flash Memory Power Control Register H FFAC Flash Memory 7 PDWND 0 R W 6 0 R 5 0 R 4 0 R 3 0 ...

Page 1103: ... pins PORT2 Port 2 Register H FFB1 Port 7 P27 R 6 P26 R 5 P25 R 4 P24 R 3 P23 R 0 P20 R 2 P22 R 1 P21 R Bit Initial value Read Write Note Determined by state of pins P27 to P20 State of the port 2 pins PORT3 Port 3 Register H FFB2 Port 7 P37 R 6 P36 R 5 P35 R 4 P34 R 3 P33 R 0 P30 R 2 P32 R 1 P31 R Bit Initial value Read Write Note Determined by state of pins P37 to P30 State of the port 3 pins ...

Page 1104: ...5 Port 5 Register H FFB4 Port 7 Undefined 6 Undefined 5 Undefined 4 Undefined 3 Undefined 0 P50 R 2 P52 R 1 P51 R Bit Initial value Read Write Note Determined by state of pins P52 to P50 State of the port 5 pins PORT9 Port 9 Register H FFB8 Port 7 P97 R 6 P96 R 5 P95 R 4 P94 R 3 P93 R 0 P90 R 2 P92 R 1 P91 R Bit Initial value Read Write Note Determined by state of pins P97 to P90 State of the port...

Page 1105: ... pins PORTB Port B Register H FFBA Port 7 PB7 R 6 PB6 R 5 PB5 R 4 PB4 R 3 PB3 R 0 PB0 R 2 PB2 R 1 PB1 R Bit Initial value Read Write Note Determined by state of pins PB7 to PB0 State of the port B pins PORTC Port C Register H FFBB Port 7 PC7 R 6 PC6 R 5 PC5 R 4 PC4 R 3 PC3 R 0 PC0 R 2 PC2 R 1 PC1 R Bit Initial value Read Write Note Determined by state of pins PC7 to PC0 State of the port C pins ...

Page 1106: ...s PORTE Port E Register H FFBD Port 7 PE7 R 6 PE6 R 5 PE5 R 4 PE4 R 3 PE3 R 0 PE0 R 2 PE2 R 1 PE1 R Bit Initial value Read Write Note Determined by state of pins PE7 to PE0 State of the port E pins PORTF Port F Register H FFBE Port 7 PF7 R 6 PF6 R 5 PF5 R 4 PF4 R 3 PF3 R 0 PF0 R 2 PF2 R 1 Undefined Bit Initial value Read Write Note Determined by state of pins PF7 to PF2 PF0 State of the port F pin...

Page 1107: ...POR1 PPG module TPU module Pulse output enable Pulse output Output compare Output PWM output enable Output compare output PWM output Input capture input WDDR1 WDR1 RDR1 RPOR1 n 0 or 1 Note Write to P1DDR Write to P1DR Read P1DR Read port 1 Legend Priority order Output compare output PWM output pulse output DR output Figure C 1 a Port 1 Block Diagram Pins P10 and P11 ...

Page 1108: ...enable Output compare output PWM output Pulse output External clock input Input capture input Legend WDDR1 Write to P1DDR WDR1 Write to P1DR RDR1 Read P1DR RPOR1 Read port 1 n 2 or 3 Note Priority order output compare output PWM output pulse output DR output Internal data bus Internal address bus Figure C 1 b Port 1 Block Diagram Pins P12 and P13 ...

Page 1109: ...0 interrupt input Output compare output PWM output enable Output compare output PWM output Pulse output Input capture input Legend WDDR1 Write to P1DDR WDR1 Write to P1DR RDR1 Read P1DR RPOR1 Read port 1 Note Priority order output compare output PWM output pulse output DR output Internal data bus Figure C 1 c Port 1 Block Diagram Pin P14 ...

Page 1110: ...e output PWM output enable Output compare output PWM output Pulse output Input capture input External clock input Legend WDDR1 Write to P1DDR WDR1 Write to P1DR RDR1 Read P1DR RPOR1 Read port 1 Note Priority order output compare output PWM output pulse output DR output Internal data bus Figure C 1 d Port 1 Block Diagram Pin P15 ...

Page 1111: ...ut compare Output PWM output enable Output compare output PWM output Pulse output Input capture input Input controller IRQ1 interrupt input Legend WDDR1 WDR1 RDR1 RPOR1 Write to P1DDR Write to P1DR Read P1DR Read port 1 Note Priority order output compare output PWM output pulse output DR output Figure C 1 e Port 1 Block Diagram Pin P16 ...

Page 1112: ...able Output compare output PWM output enable Output compare output PWM output Pulse output Input capture input External clock input Legend WDDR1 WDR1 RDR1 RPOR1 Write to P1DDR Write to P1DR Read P1DR Read port 1 Note Priority order output compare output PWM output pulse output DR output Figure C 1 f Port 1 Block Diagram Pin P17 ...

Page 1113: ...tput PWM output enable Output compare output PWM output Input capture input Internal data bus Legend WDDR2 WDR2 RDR2 RPOR2 n 0 to 3 5 and 7 Write to P2DDR Write to P2DR Read P2DR Read port 2 Note Priority order output compare output PWM output pulse output DR output Figure C 2 a Port 2 Block Diagram Pins P20 to P23 P25 and P27 ...

Page 1114: ...mpare output PWM output enable Output compare output PWM output Input capture input Internal data bus Legend WDDR2 WDR2 RDR2 RPOR2 n 4 or 6 Write to P2DDR Write to P2DR Read P2DR Read port 2 Note Priority order output compare output PWM output pulse output DR output Figure C 2 b Port 2 Block Diagram Pins P24 and P26 ...

Page 1115: ...3 TxD0 SCI module Serial transmit enable Serial transmit data Notes 1 Output enable signal 2 Open drain control signal P30DR Reset WODR3 R C Q D P30ODR 1 2 Legend WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Figure C 3 a Port 3 Block Diagram Pin P30 ...

Page 1116: ...erial receive data enable Serial receive data RxD0 P31DR Reset WODR3 R C Q D P31ODR 1 2 Notes 1 Output enable signal 2 Open drain control signal Legend WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Figure C 3 b Port 3 Block Diagram Pin P31 ...

Page 1117: ... SCK0 Interrupt controller IRQ4 interrupt input P32DR Reset WODR3 R C Q D P32ODR 2 3 1 Serial clock input SCK0 Notes 1 Priority order Serial clock output DR output 2 Output enable signal 3 Open drain control signal Legend WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Figure C 3 c Port 3 Block Diagram Pin P32 ...

Page 1118: ...Serial transmit enable Serial transmit data P33DR Reset WODR3 R C Q D P33ODR 1 2 TxD1 Notes 1 Output enable signal 2 Open drain control signal Legend WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Figure C 3 d Port 3 Block Diagram Pin P33 ...

Page 1119: ...erial receive data enable Serial receive data RxD1 P34DR Reset WODR3 R C Q D P34ODR 1 2 Notes 1 Output enable signal 2 Open drain control signal Legend WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Figure C 3 e Port 3 Block Diagram Pin P34 ...

Page 1120: ...lock output SCK1 Serial clock input enable P35DR Reset WODR3 R C Q D P35ODR 2 3 1 Serial clock input SCK1 Notes 1 Priority order IIC output Serial clock output DR output 2 Output enable signal 3 Open drain control signal Legend WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Figure C 3 f Port 3 Block Diagram Pin P35 ...

Page 1121: ...P3nODR 1 2 Reset Internal data bus Reset Reset 1 Output enable signal 2 Open drain control signal Notes Legend WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 n 6 or 7 Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Figure C 3 g Port 3 Block Diagram Pins P36 and P37 ...

Page 1122: ...1090 C 4 Port 4 Block Diagram P4n RPOR4 Internal data bus A D converter module Analog input Legend RPOR4 Read port 4 n 0 to 7 Figure C 4 Port 4 Block Diagram Pins P40 to P47 ...

Page 1123: ...C Q D WDDR5 WDR5 R C Q D P5n RDR5 RPOR5 P5nDR Reset Internal data bus Reset WDDR5 WDR5 RDR5 RPOR5 n 0 to 2 Write to P5DDR Write to P5DR Read P5DR Read port 5 Legend Figure C 5 a Port 5 Block Diagram Pins P50 to P52 H8S 2646 H8S 2646R H8S 2645 ...

Page 1124: ...OR5 P50DR Legend WDDR5 WDR5 RDR5 RPOR5 Write to P5DDR Write to P5DR Read P5DR Read port 5 Internal data bus Reset Reset SCI module Serial receive data enable Serial receive data TxD2 Figure C 5 b Port 5 Block Diagram Pin P50 H8S 2648 H8S 2648R H8S 2647 ...

Page 1125: ...OR5 P51DR Internal data bus Reset Reset SCI module Serial receive data enable Serial receive data TxD2 Legend WDDR5 WDR5 RDR5 RPOR5 Write to P5DDR Write to P5DR Read P5DR Read port 5 Figure C 5 c Port 5 Block Diagram Pin P51 H8S 2648 H8S 2648R H8S 2647 ...

Page 1126: ...DDR Write to P5DR Read P5DR Read port 5 Internal data bus Reset Reset SCI module Serial clock output enable Serial clock output SCK2 Serial clock input enable Serial clock input SCK2 Note Priority order Serial clock output DR output Figure C 5 d Port 5 Block Diagram Pin P52 H8S 2648 H8S 2648R H8S 2647 ...

Page 1127: ...1095 C 6 Port 9 Block Diagram P9n RPOR9 Internal data bus A D converter module Analog input RPOR9 n 0 to 7 Read port 9 Legend Figure C 6 Port 9 Block Diagram Pins P90 to P97 ...

Page 1128: ...DDRA R C Q D PAnDDR Reset WODRA RPCRA R C Q D PAnODR 1 2 Mode4 5 6 Address enable Notes 1 Output enable signal 2 Open drain control signal WDDRA WDRA WODRA WPCRA RDRA RPORA RODRA RPCRA n 0 to 7 Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Legend Figure C 7 Port A Block Diagram Pins PA0 to PA7 ...

Page 1129: ...DRB R C Q D PBnDDR Reset WODRB RPCRB R C Q D PBnODR 1 2 Mode 4 5 6 Address enable Notes 1 Output enable signal 2 Open drain control signal WDDRB WDRB WODRB WPCRB RDRB RPORB RODRB RPCRB n 0 to 7 Write to PBDDR Write to PBDR Write to PBODR Write to PBPCR Read PBDR Read port B Read PBODR Read PBPCR Legend Figure C 8 Port B Block Diagram Pins PB0 to PB7 ...

Page 1130: ...et WDDRA R C Q D PCnDDR Reset WODRC RPCRC R C Q D PCnODR 1 2 Mode 4 5 Mode 6 Notes 1 Output enable signal 2 Open drain control signal WDDRA WDRA WODRA WPCRA RDRA RPORA RODRA RPCRA n 0 to 7 Write to PCDDR Write to PCDR Write to PCODR Write to PCPCR Read PCDR Read port A Read PCODR Read PCPCR Legend Figure C 9 Port C Block Diagram Pins PC0 to PC7 ...

Page 1131: ...er write R C Q D PDn RDRD RPORD PDnDR WDDRD C Q D PDnDDR RPCRD Mode 7 Mode 4 5 6 External address write Reset R External address upper read WDDRD WDRD WPCRD RDRD RPORD RPCRD n 0 to 7 Write to PDDDR Write to PDDR Write to PDPCR Read PDDR Read port D Read PDPCR Legend Figure C 10 Port D Block Diagram Pins PD0 to PD7 ...

Page 1132: ...t WDRE R C Q D PEn RDRE RPORE PEnDR WDDRE C Q D PEnDDR RPCRE Mode 7 Mode 4 5 6 External address write Reset R External addres lower read WDDRE WDRE WPCRE RDRE RPORE RPCRE n 0 to 7 Write to PEDDR Write to PEDR Write to PEPCR Read PEDR Read port E Read PEPCR Legend Figure C 11 Port E Block Diagram Pins PE0 to PE7 ...

Page 1133: ...ms R PF0DDR C Q D Reset Internal data bus WDDRF Reset WDRF R C Q D PF0 RDRF RPORF IRQ interrupt input PF0DR WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F Legend Figure C 12 a Port F Block Diagram Pin PF0 ...

Page 1134: ...data bus WDDRF Reset WDRF R PF2DR C Q D PF2 RDRF RPORF Wait input Bus controller Wait enable Mode 4 5 6 Mode 4 5 6 WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F Legend Figure C 12 b Port F Block Diagram Pin PF2 ...

Page 1135: ...bus WDDRF Reset WDRF R PF3DR C Q D PF3 RDRF RPORF Bus controller ADTRG input IRQ3 interrupt input LWR output Mode 4 5 6 WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F Legend Figure C 12 c Port F Block Diagram Pin PF3 ...

Page 1136: ...t Internal data bus Mode 4 5 6 WDDRF Reset WDRF R PF4DR C Q D PF4 RDRF RPORF Bus controller HWR output WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F Legend Figure C 12 d Port F Block Diagram Pin PF4 ...

Page 1137: ...et Internal data bus WDDRF Reset Mode 4 5 6 WDRF R PF5DR C Q D PF5 RDRF RPORF Bus controller RD output WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F Legend Figure C 12 e Port F Block Diagram Pin PF5 ...

Page 1138: ...et Internal data bus WDDRF Reset Mode 4 5 6 WDRF R PF6DR C Q D PF6 RDRF RPORF Bus controller AS output WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F Legend Figure C 12 f Port F Block Diagram Pin PF6 ...

Page 1139: ...RF PF7 RDRF RPORF ø Reset Internal data bus R Mode 4 5 6 S C Q D PF7DDR Note Set priority WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F Legend Figure C 12 g Port F Block Diagram Pin PF7 ...

Page 1140: ...Reset Internal data bus WDDRH Reset WDRH R C Q D PHn RDRH RPORH PWM module PWM output enable PWM output PHnDR WDDRH WDRH RDRH RPORH n 0 to 7 Write to PHDDR Write to PHDR Read PHDR Read port H Legend Figure C 13 Port H Block Diagram Pins PH0 to PH7 ...

Page 1141: ...Reset WDDRJ Reset WDRJ R C Q D PJn RDRJ RPORJ PJnDR Internal data bus PWM module PWM output enable PWM output WDDRJ WDRJ RDRJ RPORJ n 0 to 7 Write to PJDDR Write to PJDR Read PJDR Read port J Legend Figure C 14 Port J Block Diagram Pins PJ0 to PJ7 ...

Page 1142: ...gram R PKnDDR C Q D WDDRK WDRK R C Q D PKn RDRK RPORK PKnDR Reset Reset Internal data bus WDDRK WDRK RDRK RPORK n 6 or 7 Write to PKDDR Write to PKDR Read PKDR Read port K Legend Figure C 15 Port K Block Diagram Pins PK6 and PK7 ...

Page 1143: ...ort 9 4 to 7 T T T Input port Port A 4 5 6 L T T T Address output OPE 0 T Address output OPE 1 kept Segment common output port Otherwise kept Address output A23 to A16 Segment common output SEG24 to SEG21 COM4 to COM1 Otherwise I O port 7 T T Segment common output port Otherwise kept Segment common output SEG24 to SEG21 COM4 to COM1 Otherwise I O port Port B 4 5 6 L T T T Address output OPE 0 T Ad...

Page 1144: ...0 DDR 0 Input port 7 T T Segment output port Otherwise kept Segment output SEG8 to SEG1 Otherwise I O port Port D 4 to 6 T T T Data bus 7 T T kept I O port Port E 4 to 6 8 bit bus T T kept I O port 16 bit bus T T T Data bus 7 T T kept I O port PF7 ø 4 to 6 Clock output T DDR 0 T DDR 1 H DDR 0 T DDR 1 Clock output 7 T T DDR 0 T DDR 1 H DDR 0 T DDR 1 Clock output PF6 AS 4 to 6 H T OPE 0 T OPE 1 H AS...

Page 1145: ...rt PF2 WAIT 4 to 6 T T Segment output port Otherwise kept WAITE 1 WAIT 7 T T Segment output port Otherwise kept Segment output SEG17 Otherwise I O port PF0 4 to 7 T T kept I O port Port H 4 to 7 T T kept I O port Port J 4 to 7 T T kept I O port Port K 4 to 7 T T kept I O port Legend H High level L Low level T High impedance kept Input port becomes high impedance output port retains state Port Dete...

Page 1146: ...rt Port A 4 5 6 L T T T Address output OPE 0 T Address output OPE 1 kept Segment common output port Otherwise kept Address output A23 to A16 Segment common output SEG40 to SEG37 COM4 to COM1 Otherwise I O port 7 T T Segment common output port Otherwise kept Segment common output SEG40 to SEG37 COM4 to COM1 Otherwise I O port Port B 4 5 6 L T T T Address output OPE 0 T Address output OPE 1 kept Seg...

Page 1147: ...0 DDR 0 Input port 7 T T Segment output port Otherwise kept Segment output SEG24 to SEG17 Otherwise I O port Port D 4 to 6 T T T Data bus 7 T T kept I O port Port E 4 to 6 8 bit bus T T kept I O port 16 bit bus T T T Data bus 7 T T kept I O port PF7 ø 4 to 6 Clock output T DDR 0 T DDR 1 H DDR 0 T DDR 1 Clock output 7 T T DDR 0 T DDR 1 H DDR 0 T DDR 1 Clock output PF6 AS 4 to 6 H T OPE 0 T OPE 1 H ...

Page 1148: ...rt PF2 WAIT 4 to 6 T T Segment output port Otherwise kept WAITE 1 WAIT 7 T T Segment output port Otherwise kept Segment output SEG17 Otherwise I O port PF0 4 to 7 T T kept I O port Port H 4 to 7 T T kept I O port Port J 4 to 7 T T kept I O port Port K 4 to 7 T T kept I O port Legend H High level L Low level T High impedance kept Input port becomes high impedance output port retains state Port Dete...

Page 1149: ... STBY low to RES high 0 ns or more STBY RES t2 0ns t1 10tcyc Figure E 1 Timing of Transition to Hardware Standby Mode 2 To retain RAM contents with the RAME bit cleared to 0 in SYSCR or when RAM contents do not need to be retained RES does not have to be driven low as in 1 Timing of Recovery from Hardware Standby Mode Drive the RES signal low and the NMI signal high approximately 100 ns or more be...

Page 1150: ... and H8S 2647 Hitachi Code JEDEC JEITA Mass reference value FP 144J Conforms 2 4 g Dimension including the plating thickness Base material dimension 0 10 M 20 22 0 0 2 73 36 144 0 5 0 10 3 05 Max 0 8 22 0 0 2 108 72 37 109 1 0 17 0 05 2 70 0 22 0 05 0 5 0 1 1 0 0 10 0 15 0 10 1 25 0 20 0 04 0 15 0 04 Unit mm Figure F 1 FP 144J Package Dimension H8S 2646R H8S 2648R ...

Page 1151: ...cluding the plating thickness Base material dimension 0 10 M 20 22 0 0 2 73 36 144 0 5 0 10 3 05 Max 0 8 22 0 0 2 108 72 37 109 1 0 17 0 05 2 70 0 22 0 05 0 5 0 1 1 0 0 10 0 15 0 10 1 25 0 20 0 04 0 15 0 04 Unit mm Figure F 2 FP 144G Package Dimension H8S 2646 H8S 2645 H8S 2648 H8S 2647 ...

Page 1152: ...1120 ...

Page 1153: ...e 1st Edition December 1999 4th Edition September 2002 Published by Business Operation Division Semiconductor Integrated Circuits Hitachi Ltd Edited by Technical Documentation Group Hitachi Kodaira Semiconductor Co Ltd Copyright Hitachi Ltd 1999 All rights reserved Printed in Japan ...

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