Hitachi H8S/2645, Hardware Manual

Page: 655 / 1153

623
Bits 15 to 10—Reserved: These bits cannot be read from or written to.
Bits 9 to 0—Duty (DT): Bits 9 to 0 set the PWM output duty according to the values in bits 9 to 0
in the buffer register that is transferred by a PWCYR2 compare match. A high level (or a low level
when the corresponding bit in PWPR2 is set to 1) is output from the time PWCNT2 is cleared by a
PWCYR2 compare match until a PWDTR2 compare match occurs. When all the bits are 0, there
is no high-level output period (no low-level output period when the corresponding bit in PWPR2
is set to 1).
PWCNT2
(lower 10 bits)
PWCYR2
(lower 10 bits)
PWDTR2
(lower 10 bits)
PWM output
Compare match
0 1
N
M
M–2 M–1 M N–1 0
Figure 17-6 Duty Register Compare Match (OPS = 0 in PWPR2)
0 1 N–1 0
N
M
N–2
PWCNT2
(lower 10 bits)
PWCYR2
(lower 10 bits)
PWDTR2
(lower 10 bits)
PWM output
(M = 0)
PWM output
(0
<
M
<
N)
PWM output
(N
≤
M)
Figure 17-7 Differences in PWM Output According to Duty Register Set Value
(OPS = 0 in PWPR2)