Hitachi H8S/2645, Hardware Manual

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Section 12 Watchdog Timer
12.1 Overview
The H8S/2646 Series has an on-chip watchdog timer with two channels (WDT0, WDT1). The
WDT can also generate an internal reset signal for the H8S/2646 Series if a system crash prevents
the CPU from writing to the timer counter, allowing it to overflow.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
12.1.1 Features
WDT features are listed below.
•
Switchable between watchdog timer mode and interval timer mode
•
An internal reset can be issued if the timer counter overflows.
In the watchdog timer mode, the WDT can generate an internal reset.
•
Interrupt generation when in interval timer mode
If the counter overflows, the WDT generates an interval timer interrupt.
•
WDT0 and WDT1 respectively allow eight and sixteen types of counter input clock to be
selected
The maximum interval of the WDT is given as a system clock cycle
×
131072
×
256.
A subclock may be selected for the input counter of WDT1.
Where a subclock is selected, the maximum interval is given as a subclock cycle
×
256
×
256.