Hitachi H8S/2645, Hardware Manual

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968
IER—IRQ Enable Register H'FE14 Interrupt Controller
7
—
0
R/W
6
—
0
R/W
5
IRQ5E
0
R/W
4
IRQ4E
0
R/W
3
IRQ3E
0
R/W
0
IRQ0E
0
R/W
2
IRQ2E
0
R/W
1
IRQ1E
0
R/W
Bit
Initial value
Read/Write
IRQ5 to IRQ0 Enable
(n = 5 to 0)
0 IRQn interrupts disabled
IRQn interrupts enabled 1
ISR—IRQ Status Register H'FE15 Interrupt Controller
7
—
0
R/(W)
*
6
—
0
R/(W)
*
5
IRQ5F
0
R/(W)
*
4
IRQ4F
0
R/(W)
*
3
IRQ3F
0
R/(W)
*
0
IRQ0F
0
R/(W)
*
2
IRQ2F
0
R/(W)
*
1
IRQ1F
0
R/(W)
*
Bit
Initial value
Read/Write
IRQ5 to IRQ0 Flags
0 [Clearing conditions]
• Cleared by reading IRQnF when IRQnF = 1, then writing 0 to IRQnF flag
• When interrupt exception handling is executed while low-level detection
is set (IRQnSCB = IRQnSCA = 0) and
IRQn
input is high
• When IRQn interrupt exception handling is executed while falling, rising,
or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)
• When the DTC is activated by an IRQn interrupt, and the DISEL bit in
MRB of the DTC is cleared to 0
1 [Setting conditions]
• When
IRQn
input goes low when low-level detection is set
(IRQnSCB = IRQnSCA = 0)
• When a falling edge occurs in
IRQn
input when falling edge detection is
set (IRQnSCB = 0, IRQnSCA = 1)
• When a rising edge occurs in
IRQn
input when rising edge detection is
set (IRQnSCB = 1, IRQnSCA = 0)
• When a falling or rising edge occurs in
IRQn
input when both-edge
detection is set (IRQnSCB = IRQnSCA = 1)
Note: * Only 0 can be written, to clear the flag.
(n = 5 to 0)