Hitachi H8S/2645, Hardware Manual

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23.4.3 Bus Timing
Table 23-6 lists the bus timing.
Table 23-6 Bus Timing
Condition : V
CC
= PWMV
CC
= 4.5 V to 5.5 V, LPV
CC
= 4.5 V to 5.5 V, AV
CC
= 4.5 V to 5.5 V,
V
ref
= 4.5 V to AV
CC
, V
SS
= PWMV
SS
= PLLV
SS
= AV
SS
= 0 V, T
a
= –20°C to
+75°C (regular specifications), T
a
= –40°C to +85°C (wide-range specifications)
Condition
Item Symbol Min Max Unit Test Conditions
Address delay time t
AD
— 45 ns Figure 23-7 to
Address setup time t
AS
0.5
×
t
cyc
– 32
— ns Figure 23-11
Address hold time t
AH
0.5
×
t
cyc
– 15
— ns
AS
delay time
t
ASD
— 45 ns
RD
delay time 1
t
RSD1
— 45 ns
RD
delay time 2
t
RSD2
— 45 ns
Read data setup time t
RDS
20 — ns
Read data hold time t
RDH
10 — ns
Read data access time 1 t
ACC1
—
1.0
×
t
cyc
– 60
ns
Read data access time 2 t
ACC2
—
1.5
×
t
cyc
– 50
ns
Read data access time 3 t
ACC3
—
2.0
×
t
cyc
– 60
ns
Read data access time 4 t
ACC4
—
2.5
×
t
cyc
– 50
ns
Read data access time 5 t
ACC5
—
3.0
×
t
cyc
– 60
ns
WR
delay time 1 t
WRD1
— 35 ns
WR
delay time 2 t
WRD2
— 45 ns
WR
pulse width 1 t
WSW1
1.0
×
t
cyc
– 40 — ns
WR
pulse width 2 t
WSW2
1.5
×
t
cyc
– 30 — ns
Write data delay time t
WDD
— 45 ns
Write data setup time t
WDS
0.5
×
t
cyc
– 20 — ns
Write data hold time t
WDH
0.5
×
t
cyc
– 10 — ns
WAIT
setup time t
WTS
30 — ns
WAIT
hold time t
WTH
5 — ns