Hitachi H8S/2645, Hardware Manual

Page: 8 / 1153

Section Page Description
9.13.2 Register
Configuration 283 Part F Data Register (PFDR)
Bit : 7 6 5 4 3 2 1 0
— PF6DR PF5DR PF4DR PF3DR PF2DR — PF0DR
Initial value : 000000
undefined
0
R/W : R/W R/W R/W R/W R/W R/W — R/W
2nd line changed as follows
PFDR is an 8-bit readable/writable register that stores output data for the port F
pins (PF6 to PF2, PF0).
6th line changed as follows
Bits 7 and 1 in PFDR are reserved, and only 0 may be written to it.
15.2.3 Bit
Configuration
Register (BCR) 539 Figure of Detailed Description of Timing within 1 Bit, HCAN bit rate calculation,
BCR Setting Constraints, Table of Setting Range for TSEG1 and TSEG2 in
BCR
Moved to Bit Rate and Bit Timing Settings in section 15.3.2, Initialization after
Hardware Reset.
15.2.11 Interrupt
Register (IRR) 547 Bit 15—Overload Frame Interrupt Flag: Status flag indicating that the HCAN
has transmitted an overload frame.
Bit 15: IRR7 Description
0[Clearing condition]
Writing 1 (Initial value)
1 Overload frame transmission
[Setting conditions]
When overload frame is transmitted
15.2.16 Unread
Message Status
Register (UMSR) 555 Bit table amended and Note added
UMSR
Bit: 15 14 13 12 11 109 8
UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0
Initial value: 00000000
R/W: R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) * R/(W) *
Bit: 7 6 5 4 3 2 1 0
UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10UMSR9 UMSR8
Initial value: 00000000
R/W: R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
R/(W)
*
Note: * Only 1 can be written, to clear the flag.