Hitachi H8S/2645, Hardware Manual, Page: 573 / 1153

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15.2.5 Transmit Wait Register (TXPR)
The transmit wait register (TXPR) is a 16-bit readable/writable register that is used to set a
transmit wait after a transmit message is stored in a mailbox (buffer) (CAN bus arbitration wait).
TXPR
Bit: 15 14 13 12 11 10 9 8
TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1 —
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W —
Bit: 7 6 5 4 3 2 1 0
TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8
Initial value: 0 0 0 0 0 0 0 0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bits 15 to 9 and 7 to 0—Transmit Wait Register: These bits set a transmit wait for the
corresponding mailboxes.
Bit x: TXPRx Description
0 Transmit message idle state in corresponding mailbox (Initial value)
[Clearing condition]
Message transmission completion and cancellation completion
1 Transmit message transmit wait in corresponding mailbox (CAN bus
arbitration)
(x = 15 to 0)
Bit 8—Reserved: This bit always reads 0. The write value should always be 0.