Hitachi H8S/2645, Hardware Manual

Page: 107 / 1153

75
2.9.4 On-Chip HCAN Module Access Timing
On-chip HCAN module access is performed in four states. The data bus width is 16 bits. Wait
states can be inserted by means of a wait request from the HCAN. On-chip HCAN module access
cycle is shown in figures 2-21 and 2-22, and the pin states in figure 2-23.
Internal address bus
HCAN read signal
Internal data bus
HCAN write signal
Internal data bus
ø
Bus cycle
T1
Address
Read
Write
Read data
Write data
T3
T2
T4
Figure 2-21 On-Chip HCAN Module Access Cycle (No Wait State)
Internal address bus
HCAN read signal
Internal data bus
HCAN write signal
Internal data bus
ø
Bus cycle
T1
Address
Read
Write
T3
T2
Tw
Read data
Write data
Tw T4
Figure 2-22 On-Chip HCAN Module Access Cycle (Wait States Inserted)