1012
TIOR0H—Timer I/O Control Register 0H
H'FF12
TPU0
7
IOB3
0
R/W
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
3
IOA3
0
R/W
0
IOA0
0
R/W
2
IOA2
0
R/W
1
IOA1
0
R/W
Bit
Initial value
Read/Write
*
: Don't care
TGR0A I/O Control
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down
TGR0A is
output
compare
register
TGR0A is
input
capture
register
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCA0 pin
Capture input
source is channel
1/count clock
1
0
1
0
1
0
1
*
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*
*
*
: Don't care
TGR0B I/O Control
0
0 output at compare match
1 output at compare match
Toggle output at compare match
0 output at compare match
1 output at compare match
Toggle output at compare match
Input capture at rising edge
Input capture at falling edge
Input capture at both edges
Input capture at TCNT1 count-up/
count-down
*
1
TGR0B is
output
compare
register
TGR0B is
input
capture
register
Output disabled
Initial output is 0
output
Output disabled
Initial output is 1
output
Capture input
source is
TIOCB0 pin
Capture input
source is channel
1/count clock
1
0
1
0
1
0
1
*
0
1
0
1
0
1
0
1
0
1
0
1
0
1
*
*
Note:
*
1 When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and ø/1 is used as the
TCNT1 count clock, this setting is invalid and input capture is not generated.
Summary of Contents for H8S/2645
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Page 16: ......
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Page 530: ...498 ...
Page 562: ...530 ...
Page 642: ...610 ...
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Page 812: ...780 ...
Page 837: ...805 A 2 Instruction Codes Table A 2 shows the instruction codes ...
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