Hitachi H8S/2645, Hardware Manual

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17.2.4 PWM Counters 1 and 2 (PWCNT1, PWCNT2)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — — — —
Initial value 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0
Read/Write — — — — — — — — — — — — — — — —
PWCNT is a 10-bit up-counter incremented by the input clock. The input clock is selected by
clock select bits 2 to 0 (CKS2 to CKS0) in PWCR.
PWCNT1 is used as the channel 1 time base, and PWCNT2 as the channel 2 time base.
PWCNT is initialized to H'FC00 when the counter start bit (CST) in PWCR is cleared to 0, and
also upon reset and in standby mode, watch mode, subactive mode, subsleep mode, and module
stop mode.
17.2.5 PWM Cycle Registers 1 and 2 (PWCYR1, PWCYR2)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
— — — — — —
Initial value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Read/Write — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
PWCYR is a 16-bit read/write register that sets the PWM conversion cycle. When a PWCYR
compare match occurs, PWCNT is cleared and data is transferred from the buffer register
(PWBFR) to the duty register (PWDTR). PWCYR1 is used for the channel 1 conversion cycle
setting, and PWCYR2 for the channel 2 conversion cycle setting.
PWCYR should be written to only while PWCNT is stopped. A value of H'FC00 must not be set.
PWCYR is initialized to H'FFFF upon reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
0 1 0 1
N
N–1
PWCNT
(lower 10 bits)
PWCYR
(lower 10 bits)
N–2
Compare match Compare match
Figure 17-3 Cycle Register Compare Match