Hitachi H8S/2645, Hardware Manual

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9.8.2 Register Configuration
Table 9-12 shows the port A register configuration.
Table 9-12 Port A Registers
Name Abbreviation R/W Initial Value Address
*
Port A data direction register PADDR W H'00 H'FE39
Port A data register PADR R/W H'00 H'FF09
Port A register PORTA R Undefined H'FFB9
Port A MOS pull-up control register PAPCR R/W H'00 H'FE40
Port A open-drain control register PAODR R/W H'00 H'FE47
Note: * Lower 16 bits of the address.
Port A Data Direction Register (PADDR)
Bit : 7 6 5 4 3 2 1 0
PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
Initial value : 0 0 0 0 0 0 0 0
R/W : W W W W W W W W
PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port A. PADDR cannot be read; if it is, an undefined value will be read.
PADDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode. The OPE bit in SBYCR is used to select whether the address output pins
retain their output state or become high-impedance when a transition is made to software standby
mode.
•
Modes 4 to 6
These function as segment pins if the values of bits SGS3 to SGS0 of LPCR, the LCD driver,
are other than B'0000. If the value of bits SGS3 to SGS0 is B'0000, the port A pins function as
address outputs as specified by the setting of bits AE3 to AE0 of PFCR, regardless of the
values of bits PA7DDR to PA0DDR. Also, when the pins are not used as address outputs,
setting a PADDR bit to 1 makes the corresponding port A pin an output port, and clearing a bit
to 0 makes the corresponding pin an input port.
•
Mode 7
These function as segment pins if the values of bits SGS3 to SGS0 of LPCR, the LCD driver,
are other than B'0000. If the value of bits SGS3 to SGS0 is B'0000, setting a PADDR bit to 1
makes the corresponding port A pin an output port, and clearing a bit to 0 makes the
corresponding pin an input port.