Hitachi H8S/2645, Hardware Manual

Page: 315 / 1153

283
Port F Data Register (PFDR)
Bit : 7 6 5 4 3 2 1 0
— PF6DR PF5DR PF4DR PF3DR PF2DR — PF0DR
Initial value : 0 0 0 0 0 0
undefined
0
R/W : R/W R/W R/W R/W R/W R/W — R/W
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF6 to PF2,
PF0).
PFDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in
software standby mode.
Bits 7 and 1 in PFDR are reserved, and only 0 may be written to it.
Port F Register (PORTF)
Bit : 7 6 5 4 3 2 1 0
PF7 PF6 PF5PF4 PF3 PF2 — PF0
Initial value : — * — * — * — * — * — *
undefined
— *
R/W : R R R R R R — R
Note:
*
Determined by state of pins PF7 to PF2, PF0.
PORTF is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of
output data for the port F pins (PF7 to PF2, PF0) must always be performed on PFDR.
If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F
read is performed while PFDDR bits are cleared to 0, the pin states are read.
Pins used as LCD driver pins will return an undefined value if read.
After a reset and in hardware standby mode, PORTF contents are determined by the pin states, as
PFDDR and PFDR are initialized. PORTF retains its prior state in software standby mode.
PORTF bit 1 is reserved.