Hitachi H8S/2645, Hardware Manual

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BCRA—Break Control Register A H'FE08 PBC
BCRB—Break Control Register B H'FE09PBC
Break Condition Select
0
Instruction fetch is used as break condition
Data read cycle is used as break condition
Data write cycle is used as break condition
Data read/write cycle is used as break condition
0
1
1 0
1
7
CMFA
0
R/(W) *
6
CDA
0
R/W
5
BAMRA2
0
R/W
4
BAMRA1
0
R/W
3
BAMRA0
0
R/W
0
BIEA
0
R/W
2
CSELA1
0
R/W
1
CSELA0
0
R/W
Bit
Initial value
Read/Write
Break Address Mask Register
0 All BARA bits are unmasked and included in break conditions
BAA0 (lowest bit) is masked, and not included in break conditions
BAA1–0 (lower 2 bits) are masked, and not included in break conditions
BAA2–0 (lower 3 bits) are masked, and not included in break conditions
BAA3–0 (lower 4 bits) are masked, and not included in break conditions
BAA7–0 (lower 8 bits) are masked, and not included in break conditions
BAA11–0 (lower 12 bits) are masked, and not included in break conditions
BAA15–0 (lower 16 bits) are masked, and not included in break conditions
0
1
0
1
0
1
1 0
1
0
1
0
1
Break Interrupt Enable
0 PC break interrupts are disabled
PC break interrupts are enabled 1
CPU Cycle/DTC Cycle Select A
0 PC break is performed when CPU is bus master
PC break is performed when CPU or DTC is bus master 1
Condition Match Flag A
0 [Clearing condition]
When 0 is written to CMFA after reading CMFA = 1
[Setting condition]
When a condition set for channel A is satisfied 1
Notes: BCRB is the channel B break control register.
The bit configuration is the same as for BCRA.
*
Only a 0 may be written to this bit to clear the flag.