887
MBIMR—Mailbox Interrupt Mask Register
H'F814
HCAN
15
MBIMR7
1
R/W
14
MBIMR6
1
R/W
13
MBIMR5
1
R/W
12
MBIMR4
1
R/W
11
MBIMR3
1
R/W
8
MBIMR0
1
R/W
10
MBIMR2
1
R/W
9
MBIMR1
1
R/W
7
MBIMR15
1
R/W
6
MBIMR14
1
R/W
5
MBIMR13
1
R/W
4
MBIMR12
1
R/W
3
MBIMR11
1
R/W
0
MBIMR8
1
R/W
2
MBIMR10
1
R/W
1
MBIMR9
1
R/W
Bit
Initial value
Read/Write
Bit
Initial value
Read/Write
Mailbox Interrupt Mask
0
[Transmitting]
Interrupt request to CPU due to TXPR clearing
[Receiving]
Interrupt request to CPU due to RXPR setting
1
Interrupt requests to CPU disabled
Summary of Contents for H8S/2645
Page 4: ......
Page 16: ......
Page 58: ...26 ...
Page 110: ...78 ...
Page 120: ...88 ...
Page 132: ...100 ...
Page 160: ...128 ...
Page 172: ...140 ...
Page 418: ...386 ...
Page 444: ...412 ...
Page 530: ...498 ...
Page 562: ...530 ...
Page 642: ...610 ...
Page 662: ...630 ...
Page 688: ...656 ...
Page 756: ...724 ...
Page 784: ...752 ...
Page 812: ...780 ...
Page 837: ...805 A 2 Instruction Codes Table A 2 shows the instruction codes ...
Page 1152: ...1120 ...