Hitachi H8S/2645, Hardware Manual

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22.2.4 Timer Control/Status Register (TCSR)
7
OVF
0
R/(W)
*
6
WT/IT
0
R/W
5
TME
0
R/W
4
PSS
0
R/W
3
RST/NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Bit
Initial value
R/W
:
:
:
Note:
*
Only write 0 to clear the flag.
TCSR is an 8-bit read/write register that selects the clock input to WDT1 TCNT and the mode.
Here, we describe bit 4. For details of the other bits in this register, see section 12.2.2, Timer
Control/Status Register (TCSR).
The TCSR is initialized to H'00 at a reset and when in hardware standby mode. It is not initialized
in software standby mode.
Bit 4—Prescaler select (PSS): This bit selects the clock source input to WDT1 TCNT.
It also controls operation when shifting low power dissipation modes. The operating mode
selected after the SLEEP instruction is executed is determined in combination with other control
bits.
For details, see the description for clock selection in section 12.2.2, Timer Control/Status Register
(TCSR), and this section.
Bit 4
PSS Description
0
•
TCNT counts the divided clock from the ø -based prescaler (PSM).
•
When the SLEEP instruction is executed in high-speed mode or medium-speed
mode, operation shifts to sleep mode or software standby mode. (Initial value)
1
•
TCNT counts the divided clock from the øsubclock-based prescaler (PSS).
•
When the SLEEP instruction is executed in high-speed mode or medium-speed
mode, operation shifts to sleep mode, watch mode
*
, or sub-active mode
*
.
•
When the SLEEP instruction is executed in sub-active mode, operation shifts to sub-
sleep mode, watch mode, or high-speed mode.
Note:
*
Always set high-speed mode when shifting to watch mode or sub-active mode.