172
T
1
Address bus
ø
AS
Data bus
T
2
T
3
T
1
T
2
T
1
Full access
T
2
RD
Burst access
Low address only changes
Read data
Read data
Read data
Figure 7.14 (a) Example Burst ROM Access Timing (AST0=BRSTS1=1)
T
1
Address bus
ø
AS
Data bus
T
2
T
1
T
1
Full access
RD
Burst access
Low address only changes
Read data
Read data Read data
Figure 7.14 (b) Example Burst ROM Access Timing (AST0=BRSTS1=0)
Summary of Contents for H8S/2645
Page 4: ......
Page 16: ......
Page 58: ...26 ...
Page 110: ...78 ...
Page 120: ...88 ...
Page 132: ...100 ...
Page 160: ...128 ...
Page 172: ...140 ...
Page 418: ...386 ...
Page 444: ...412 ...
Page 530: ...498 ...
Page 562: ...530 ...
Page 642: ...610 ...
Page 662: ...630 ...
Page 688: ...656 ...
Page 756: ...724 ...
Page 784: ...752 ...
Page 812: ...780 ...
Page 837: ...805 A 2 Instruction Codes Table A 2 shows the instruction codes ...
Page 1152: ...1120 ...