Hitachi H8S/2645, Hardware Manual

Page: 782 / 1153

750
22.11 Direct Transitions
22.11.1 Overview of Direct Transitions
There are three modes, high-speed, medium-speed, and sub-active, in which the CPU executes
programs. When a direct transition is made, there is no interruption of program execution when
shifting between high-speed and sub-active modes. Direct transitions are enabled by setting the
LPWRCR DTON bit to 1, then executing the SLEEP instruction. After a transition, direct
transition interrupt exception processing starts.
Direct Transitions from High-Speed Mode to Sub-Active Mode: Execute the SLEEP
instruction in high-speed mode when the SBYCR SSBY bit = 1, LPWRCR LSON bit = 1, and
DTON bit = 1, and TSCR (WDT1) PSS bit = 1 to make a transition to sub-active mode.
Direct Transitions from Sub-Active Mode to High-Speed Mode: Execute the SLEEP
instruction in sub-active mode when the SBYCR SSBY bit = 1, LPWRCR LSON bit = 0, and
DTON bit = 1, and TSCR (WDT1) PSS bit = 1 to make a direct transition to high-speed mode
after the time set in SBYCR STS2 to STS0 has elapsed.
22.12 ø Clock Output Disabling Function
Output of the ø clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the ø clock stops at the end of the bus cycle,
and ø output goes high. ø clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, ø clock output is disabled and input port mode is set.
Table 22-6 shows the state of the ø pin in each processing state.
Table 22-6 ø Pin State in Each Processing State
DDR0 1 1
PSTOP — 0 1
Hardware standby mode High impedance High impedance High impedance
Software standby mode, watch
mode, and direct transition High impedance Fixed high Fixed high
Sleep mode and sub-sleep mode High impedance ø output Fixed high
High-speed mode, medium-speed
mode High impedance ø output Fixed high
Sub-active mode High impedance ø
SUB
output Fixed high