81
3.2.2
System Control Register (SYSCR)
7
MACS
0
R/W
6
—
0
—
5
INTM1
0
R/W
4
INTM0
0
R/W
3
NMIEG
0
R/W
0
RAME
1
R/W
2
—
0
R/W
1
—
0
—
Bit
Initial value
R/W
:
:
:
SYSCR is an 8-bit readable-writable register that selects saturating or non-saturating calculation
for the MAC instruction, selects the interrupt control mode, selects the detected edge for NMI, and
enables or disenables on-chip RAM.
SYSCR is initialized to H'01 by a reset and in hardware standby mode. SYSCR is not initialized in
software standby mode.
Bit 7—MAC Saturation (MACS): Selects either saturating or non-saturating calculation for the
MAC instruction.
Bit 7
MACS
Description
0
Non-saturating calculation for MAC instruction
(Initial value)
1
Saturating calculation for MAC instruction
Bit 6—Reserved: This bit is always read as 0 and cannot be modified.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control
mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1,
Interrupt Control Modes and Interrupt Operation.
Bit 5
Bit 4
Interrupt
INTM1
INTM0
Control Mode
Description
0
0
0
Control of interrupts by I bit
(Initial value)
1
—
Setting prohibited
1
0
2
Control of interrupts by I2 to I0 bits and IPR
1
—
Setting prohibited
Summary of Contents for H8S/2645
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Page 837: ...805 A 2 Instruction Codes Table A 2 shows the instruction codes ...
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