Hitachi H8S/2645, Hardware Manual

Page: 88 / 1153

56
Type Instruction Size
* 1
Function
Block data
transfer
instruction EEPMOV.B
EEPMOV.W
—
—
if R4L
≠
0 then
Repeat @ER5+
→
@ER6+
R4L–1
→
R4L
Until R4L = 0
else next;
if R4
≠
0 then
Repeat @ER5+
→
@ER6+
R4–1
→
R4
Until R4 = 0
else next;
Transfers a data block according to parameters set in
general registers R4L or R4, ER5, and ER6.
R4L or R4: size of block (bytes)
ER5: starting source address
ER6: starting destination address
Execution of the next instruction begins as soon as the
transfer is completed.
Notes:
*
1 Size refers to the operand size.
B: Byte
W: Word
L: Longword
*
2 Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
2.6.4 Basic Instruction Formats
The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation
field (op field), a register field (r field), an effective address extension (EA field), and a condition
field (cc).
(1) Operation Field: Indicates the function of the instruction, the addressing mode, and the
operation to be carried out on the operand. The operation field always includes the first four bits of
the instruction. Some instructions have two operation fields.
(2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data
registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register
field.
(3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute
address, or a displacement.
(4) Condition Field: Specifies the branching condition of Bcc instructions.