162
8-Bit 3-State Access Space: Figure 7-6 shows the bus timing for an 8-bit 3-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used.
The
LWR
pin is fixed high. Wait states can be inserted.
Bus cycle
T
1
T
2
Address bus
ø
AS
RD
D15 to D8
Valid
D7 to D0
Invalid
Read
HWR
LWR
D15 to D8
Valid
D7 to D0
High impedance
Write
High
T
3
Figure 7-6 Bus Timing for 8-Bit 3-State Access Space
Summary of Contents for H8S/2645
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