Hitachi H8S/2645, Hardware Manual

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1066
TCSR1—Timer Control/Status Register 1 H'FFA2(W), H'FFA2(R) WDT1
Bit
Initial value
Read/Write
7
OVF
0
R/(W) *
6
WT/
IT
0
R/W
5
TME
0
R/W
4
PSS
0
R/W
3
RST/
NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Timer Enable
0 TCNT is initialized to H'00 and halted
TCNT counts 1
Overflow Flag
0
1
Note: * Only a 0 may be written to this bit to clear the flag.
TCSR1 register differs from other registers in being more difficult to write to.
For details see section 12.2.4, Notes on Register Access.
Timer Mode Select
0 Interval timer mode: WDT1 requests an interval timer interrupt (WOVI) from the CPU when the TCNT overflows
Watchdog timer mode: WDT1 requests a reset or an NMI interrupt from the CPU when the TCNT overflows 1
Prescaler Select
0 The TCNT counts frequency-
division clock pulses of the
ø based prescaler (PSM)
The TCNT counts frequency-
division clock pulses of the
ø SUB-based prescaler (PSS)
1
Reset or NMI
0 NMI request
Internal reset request 1
Clock Select 2 to 0
ø/2
ø/64
ø/128
ø/512
ø/2048
ø/8192
ø/32768
ø/131072
øSUB/2
øSUB/4
øSUB/8
øSUB/16
øSUB/32
øSUB/64
øSUB/128
øSUB/256
25.6
µ
s
819.2
µ
s
1.6 ms
6.6 ms
26.2 ms
104.9 ms
419.4 ms
1.68 s
15.6 ms
31.3 ms
62.5 ms
125 ms
250 ms
500 ms
1 s
2 s
0
CKS2
0
PSS CKS1 CKS0 Clock Overflow Period *
(where ø = 20 MHz)
(where ø SUB = 32.768 kHz)
1
0
1
0
1
0
1
0
1
0
1
0
0 1
1
0
1
0
1
0
1
0
1
0
1
1
0
1
Note: * An overflow period is the time interval between the start of
counting up from H'00 on the TCNT and the occurrence of a
TCNT overflow.
[Clearing conditions]
•
Cleared when 0 is written to the TME bit (Only applies to WDT1)
•
Cleared by reading TCSR when OVF = 1, then write 0 in OVF
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog timer mode,
OVF is cleared automatically by the internal reset)