Hitachi H8S/2645, Hardware Manual

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17.2 Register Descriptions
17.2.1 PWM Control Registers 1 and 2 (PWCR1, PWCR2)
Bit 7 6 5 4 3 2 1 0
— — IE CMF CST CKS2 CKS1 CKS0
Initial value 1 1 0 0 0 0 0 0
Read/Write — — R/W R/(W) * R/W R/W R/W R/W
Note:
*
Only 0 can be written, to clear the flag.
PWCR is an 8-bit read/write register that performs interrupt enabling, starting/stopping, and
counter (PWCNT) clock selection. It also contains a flag that indicates a compare match with the
cycle register (PWCYR). PWCR1 is the channel 1 register, and PWCR2 is the channel 2 register.
PWCR is initialized to H'C0 upon reset, and in standby mode, watch mode, subactive mode,
subsleep mode, and module stop mode.
Bits 7 and 6—Reserved: Bits 7 and 6 are reserved; they are always read as 1 and cannot be
modified.
Bit 5—Interrupt Enable (IE): Bit 5 selects enabling or disabling of an interrupt in the event of a
compare match with the PWCYR register for the corresponding channel.
Bit 5: IEDescription
0 Interrupt disabled (Initial value)
1 Interrupt enabled
Bit 4—Compare Match Flag (CMF): Bit 4 indicates the occurrence of a compare match with the
PWCYR register for the corresponding channel.
Bit 4: CMF Description
0 [Clearing conditions] (Initial value)
•
When 0 is written to CMF after reading CMF = 1
•
When the DTC is activated by a compare match interrupt, and the DISEL bit in
the DTC’s MRB register is 0
1 [Setting condition]
When PWCNT = PWCYR