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Do not use the first random number generated after RNGEN bit is set, and it
should be saved for comparison with the next random number. Each random
number needs to be compared with the previous random number. If any pair is
equal, it means that the continuous random number generator test fails.
Error state
Clock error
When a clock error occurs because the PLLCLK48 clock is incorrect, RNG
cannot generate random numbers again. Check whether the clock controller is
configured correctly to provide RNG clock and clear CLKERINT bit. RNG can
work normally when CLKERCSTS=0. The clock error does not affect the last
random number, so the random number in RNG_DATA register can be used.
Seed error
In case of a seed error, the interrupt random number will be generated as long
as FSCSTS=1. Since the entropy may be insufficient, if there are already data in
RNG_DATA register, the generated interrupt random number cannot be used.
RNGEN bit shall be set after FSINT bit is cleared to reinitialize and restart RNG.
Register address mapping
Table 162 RNG Register Address Mapping
Register name
Description
Offset address
RNG_CTRL
RNG control register
0x00
RNG_STS
RNG state register
0x04
RNG_DATA
RNG data register
0x08
Register functional description
RNG control register (RNG_CTRL)
Offset address: 0x00
Reset value: 0x0000 0000
Field
Name
R/W
Description
1:0
Reserved
2
RNGEN
R/W
RNG Enable
0: Disable
1: Enable
3
INTEN
R/W
Interrupt Enable
0: Disable
1: Enable; when any of DATARDY bit, CLKERINT bit and FSINT bit in
RNG_STS register is set to 1, an interrupt will be pending
