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Field
Name
R/W
Description
1: The priority of Rx is higher than that of Tx
6:2
DSL
R/W
Descriptor Skip Length
This bit specifies the number of Word, Dword, or Lword skipped
between two unlinked descriptors Address skip starts from the end of
the current descriptor to the beginning of the next descriptor. When the
DSL value is equal to 0, DMA will regard the descriptor table as
continuous in ring mode.
7
EDFEN
R/W
Enhanced Descriptor Format Enable
When this bit is set, enable the enhanced descriptor format and
increase the descriptor size to 32 bytes. If the timestamp function or
IPv4 checksum offload has been activated, this bit must be set to 1.
13:8
PBL
R/W
Programmable Burst Length
These bits indicate the maximum number of beats to be transmitted in
a DMA transaction. This is the maximum value used in a single block
read and write. Each time the burst transmission is started on the host
bus, DMA will always attempt to follow the burst specified in PBL. PBL
can be programmed with allowable value 1, 2, 4, 8, 16 and 32. Any
other value may result in undefined behaviors. When USP is set to
high level, the PBL value is only applicable to Tx DMA transactions.
The PBL value has the following limitations: the maximum number of
possible beats is limited by the size of Tx FIFO and Rx FIFO of MTL
layer and the width of data bus on DMA. FIFO has a limitation, namely,
the maximum beat supported is half the FIFO depth unless specified.
15:14
PR
R/W
Priority Ratio
These bits control the priority ratio of weighted round robin arbitration
between Rx direct memory access and Tx direct memory access.
These bits are valid only when bit [1] is reset.
00: Priority ratio is 1:1
01: Priority ratio is 2:1
10: Priority ratio is 3:1
11: Priority ratio is 4:1
16
FB
R/W
Fixed Burst
This bit controls whether the AHB main interface performs fixed burst
transmission. After it is set, at the beginning of normal burst
transmission, the AHB interface only uses SINGLE, INCR4, INCR8 or
INCR16. When it is reset, the AHB interface uses single and INCR
burst transmission operations.
22:17
RPBL
R/W
Receive DMA programmable burst length (Rx DMA PBL)
This bit field indicates the maximum number of beats to transmitted in
a Rx DMA transaction. This is the maximum value used in a single
block read and write.
Each time the burst transmission is started on the host bus, Rx DMA
will always attempt to follow the burst specified in RPBL. RPBL can be
programmed with allowable value 1, 2, 4, 8, 16 and 32. Any other
value may result in undefined behaviors.
This field is valid only when USP is set to high level.
23
USP
R/W
Use Separate PBL
When set to high level, this bit configures Rx DMA using the value
configured in bit [22:17] as PBL. The PBL value in bit [13:8] is
applicable only to Tx DMA operations.
