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System architecture
Full name and abbreviation description of terms
Table 4 Full name and abbreviation description of terms
Full name in English
English abbreviation
Advanced High-Performance Bus
AHB
Advanced Peripheral Bus
APB
Core Couple Memory
CCM
System architecture block diagram
Arm
®
Cortex
®
-M4 core in the product has FPU, while the FPU of other series of
products (unless otherwise specified) is beyond the core.
The system mainly consists of eight master modules and seven slave modules.
The master modules are I-bus, D-bus and S-bus of Arm
®
Cortex
®
-M4 core with
FPU, general-purpose DMA1, general-purpose DMA2, and DMA2 peripheral
bus, Ethernet DMA bus and USB OTG HS DMA bus.
The slave modules are internal Flash I-bus, D-bus, main internal memory
SRAM1, auxiliary internal memory SRAM2, AHB1 bus and AHB1/APB bridge
connected peripherals, peripherals on AHB2 bus and EMMC.
The bus matrix provides a platform to support the master module to access the
slave module. The matrix can realize concurrent access, and the CPU still has
efficient processing capacity when multiple peripherals are running at high
speed.
It also has a 64-bit core couple memory, and it can access only through CPU.
The name and description of the bus are shown in the following table.
Table 5 Bus Name
Name
Description
I-bus
Connect the instruction bus of Arm
®
Cortex
®
-M4 core and the bus matrix.
Used for obtaining instructions.
D-bus
Connect the data bus of Arm
®
Cortex
®
-M4 core and the bus matrix.
Used for text loading and debugging access.
S-bus
Connect the system bus of Arm
®
Cortex
®
-M4 core and the bus matrix.
Used for accessing the data in peripherals and SRAM.
DMA memory bus
Connect the main interface of DMA memory and the bus matrix.
Realize transmission related to the memory through DMA.
