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Field
Name
R/W
Description
9
TSTIM
R/W
Time Stamp Trigger Interrupt Mask
If this bit is set to 1, generation of timestamp interrupts will be
disabled.
15:10
Reserved
MAC address 0 high register (MAC_ADDR0H)
Offset address: 0x40
Reset value: 0x0010 FFFF
Field
Name
R/W
Description
15:0
ADDR0H
R/W
MAC address 0 high bit [47:32]
It contains the first 16 bits (47:32) of the first 6 bytes of MAC address
0. The MAC uses this field to filter the received frames and inserts the
MAC address in the transmission flow control (pause) frame.
30:16
Reserved
31
AL1
R
Always 1
MAC address 0 low register (MAC_ADDR0L)
Offset address: 0x44
Reset value: 0xFFFF FFFF
Field
Name
R/W
Description
31:0
ADDR0L
R/W
MAC Address 0 low bit [31:0] (MAC Address 1)
This bit field contains the low 32 bits of the first 6-byte MAC address
0. This is the frame used by MAC to filter the received frames and
insert the MAC address in the transmission flow control (pause)
frame.
MAC address 1 high register (MAC_ADDR1H)
Offset address: 0x48
Reset value: 0x0000 FFFF
Field
Name
R/W
Description
15:0
ADDR1H
R/W
MAC address 1 high bit [47:32]
It contains the first 16 bits (47:32) of the first 6-byte MAC address 1.
The MAC uses this field to filter the received frames and inserts the
MAC address in the transmission flow control (pause) frame.
23:16
Reserved
29:24 MASKBCTRL
R/W
Mask Byte Control
These bits are used to compare the mask control bits of 1 byte of
each MAC address. When they are set to high level, the MAC core
will not compare the corresponding bytes of the received DA/SA
with the contents of the MAC address 1 register. Each bit is used to
control the mask of bytes, as follows:
Bit 29: ADDR1H [15:8]
Bit 28: ADDR1H [7:0]
Bit 27: ADDR1L [31:24]
…
