www.geehy.com Page 281
Field
Name
R/W
Description
19:16
YRU
R/W Year Ones Unit in BCD Format Setup
23:20
YRT
R/W Year Ten's Place Unit in BCD Format Setup
31:24
Reserved
RTC control register (RTC_CTRL)
The bits 7, 6 and 4 of this register can be written only in initialization
mode.
It is not recommended to rewrite this register when the number of hours
in the date increases, which is because the correct increment of hours
may be masked.
The written values of STCCFG and WTCCFG will take effect from next
second.
This register is under write protection.
Offset address: 0x08
Reset value of backup domain: 0x0000 0000
System reset: 0xXXXX XXXX
Field
Name
R/W
Description
2:0
WUCLKSEL R/W
Wakeup Clock Select
000
：
RTC/16
001
：
RTC/8
010
：
RTC/4
011
：
RTC/2
10x: clk_spre (usually 1Hz)
11x: clk_spre (usually 1Hz) and add 216 to WUAUTORE counter
value
3
TSETECFG R/W
Time Stamp Event Trigger Edge Configure
This bit indicates that RTC_TS generates a timestamp event on rising
edge or falling edge.
0: Rising edge
1: Falling edge
This bit can be changed only when TSEN=0.
4
RCLKDEN
R/W
RTC_REFIN reference clock detection enable
0: Disable
1: Enable
SPSC must be 0x00FF.
5
RCMCFG
R/W
Read Calendar Value Mode Configure
0: The date value is read from the shadow register, and the shadow
register is updated every two RTCCLK cycles
1, read the date value from the date register
If the clock frequency of APB1 is lower than seven times of RTCCLK
frequency, RCMCFG must be set to 1.
